Dual Synchronous Ethernet Line Card Short Form Datasheet PLL IDT82V3396 Supports manual and automatic selected input clock switch FEATURES Supports automatic hitless selected input clock switch on clock fail- HIGHLIGHTS ure Dual PLL chip: Supports three types of input clock sources: recovered clock from Provides node clock for ITU-T G.8261/G.8262 Synchronous STM-N or OC-n, PDH network synchronization timing and external Ethernet (SyncE) synchronization reference timing Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-4) jitter Provides a 2 kHz, 4 kHz, or 8 kHz frame sync input signal, and a 2 generation requirements kHz or 8 kHz frame sync output signals Provides node clocks for Cellular and WLL base-station (GSM Provides a 1PPS sync input signal and a 1PPS sync output signal and 3G networks) Provides output clocks for BITS, GPS, 3G, GSM, etc. Provides clocks for 1 Gigabit and 10 Gigabit Ethernet applica- Supports PECL/LVDS and CMOS input/output technologies tions Supports master clock calibration Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE, MAIN FEATURES ITU-T G.812, ITU-T G.8262. ITU-T G.813 and ITU-T G.783 Recom- Employs PLL architecture to feature excellent jitter performance mendations and minimize the number of external components Integrates 2 DPLLs one can be used on the transmit path and the OTHER FEATURES other on the receive path I2C and Serial microprocessor interface modes Supports programmable DPLL bandwidth: 18 Hz, 35 Hz, 70 Hz and IEEE 1149.1 JTAG Boundary Scan 560 Hz Single 3.3 V operation with 5 V tolerant CMOS I/Os Provides OUT1~OUT6 output clock frequencies up to 644.53125 72-pin QFN package, green package options available MHz APPLICATIONS Includes 25MHz, 125 MHz and 156.25 MHz for CMOS outputs 1 Gigabit Ethernet and 10 Gigabit Ethernet Includes 25.78125MHz, 128.90625 MHz and 161.1328125 MHz BITS / SSU for CMOS outputs SMC / SEC (SONET / SDH) Includes 25MHz, 125 MHz, 156.25 MHz, 312.5 MHz and 625 DWDM cross-connect and transmission equipment MHz for differential outputs Synchronous Ethernet equipment Includes 25.78125 MHz, 128.90625 MHz, 161.1328125 MHz, Central Office Timing Source and Distribution 322.265625 MHz and 644.53125 MHz for differential outputs Core and access IP switches / routers Provides IN1~IN6 input clock frequencies cover from 2 kHz to Gigabit and Terabit IP switches / routers 156.25 MHz IP and ATM core switches and access equipment Supports Forced or Automatic operating mode switch controlled by Cellular and WLL base-station node clocks an internal state machine. It supports Free- Run, Locked and Hold- Broadband and multi-service access equipment over modes The Short Form Datasheet presented herein represents a product currently in design or being considered for design. The noted characteristics are design targets. Integrated Device Technologies, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 February 4, 2013 2013 Integrated Device Technology, Inc. DSC-7238/-IDT82V3396 SHORT FORM DATASHEET DUAL SYNCHRONOUS ETHERNET LINE CARD PLL DESCRIPTION The IDT82V3396 Dual Synchronous Ethernet Line Card PLL is used term frequency accuracy of the selected input reference. In Holdover to synchronize line cards in Synchronous Ethernet and SONET/SDH mode the DPLL uses frequency data acquired while in Locked mode to equipment, and in wireless base stations. The two independent timing generate accurate frequencies for short periods. paths allow the device to simultaneously synchronize transmit interfaces The IDT82V3396 requires a 12.8 MHz master clock for its reference with the selected system backplane clock, and provide a recovered monitors and other digital circuitry. The frequency accuracy of the mas- clock from a selected receive interface to the system backplane. ter clock determines the frequency accuracy of the DPLLs in Free-Run The IDT82V3396 accepts up to 6 input references operating at com- mode. The frequency stability of the master clock determines the fre- mon Ethernet, SONET/SDH and PDH frequencies as well as other fre- quency stability of the DPLLs in Free-Run mode and in Holdover mode. quencies. The references are continually monitored for loss of signal The clocks synthesized by the IDT82V3392 DPLLs can be passed and for frequency offset per user programmed thresholds. The active through one of the two independent jitter attenuating APLLs (for jitter reference for each of the two Digital PLLs (DPLLs) is determined by sensitive applications). Any of the DPLL or APLL clocks can be routed forced selection or by automatic selection based on user programmed through a mux to any of the six clock outputs via independent output priorities and locking allowances and based on the reference monitors. dividers. The two IDT82V3396 timing paths are defined by independent The IDT82V3392 accepts sync pulse inputs that are associated with DPLLs with embedded clock synthesizers. Both DPLLs support three input references the sync pulses can have frequencies of 1 Hz, 2 kHz or primary operating modes: Free-Run, Locked and Holdover. In Free-Run 8 kHz. The device aligns its output sync pulses with the selected input mode the DPLLs generate clocks based on the master clock alone. In sync pulse. Locked mode the DPLLs filter reference clock jitter with one of the fol- All IDT82V3392 read/write registers are accessed through a SPI/I2C lowing selectable bandwidths: 18 Hz, 35 Hz, 70 Hz or 560 Hz. In Locked microprocessor interface. mode the long-term DPLL frequency accuracy is the same as the long Description 2 February 4, 2013