EMIF01-10005W5 STMicroelectronics

EMIF01-10005W5 EMI FILTER Application Specific Discretes TM INCLUDING ESD PROTECTION A.S.D. MAIN APPLICATIONS Where EMI filtering in ESD sensitive equipment is required : Computers and printers Communication systems Mobile phones MCU Boards DESCRIPTION The EMIF01-10005W5 is a highly integrated array SOT323-5L designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. Additionally, this filter includes an ESD protection circuitry FUNCTIONAL DIAGRAM which prevents the protected device from destruction when subjected to ESD surges up to 15 kV. BENEFITS I1 O1 Cost-effectiveness compared to discrete solution EMI bi-directional low-pass filter High efficiency in ESD suppression. GND High flexibility in the design of high density boards 2 Very low PCB space consuming : 4.2 mm typically High reliability offered by monolithic integration I2 O2 COMPLIES WITH THE FOLLOWING STANDARD: RI/O = 100 IEC 1000-4-2 15kV (air discharge) 8 kV (contact discharge) CIN = 50pF ESD response to IEC1000-4-2 (16 kV air discharge) Filtering response dB 0 -10 -20 f(MHz) -30 1 10 100 1000 2000 TM : ASD is trademark of STMicroelectronics. May 1999 - Ed: 1 1/10EMIF01-10005W5 ABSOLUTE MAXIMUM RATINGS (Tamb = 25 C) Symbol Parameter and test conditions Value Unit VPP ESD discharge IEC1000-4-2, air discharge 16 kV ESD discharge IEC1000-4-2, contact discharge 9 T Junction temperature 150 C j Top Operating temperature range -40 to + 85 C T Storage temperature range -55 to +150 C stg T Lead solder temperature (10 second duration) 260 C L ELECTRICAL CHARACTERISTICS (T = 25 C) amb Symbol Parameter I V Breakdown voltage BR IRM Leakage current VRM V Stand-off voltage RM V V V CL BR RM V Clamping voltage CL V I RM I R Rd Dynamic impedance I Peak pulse current PP slope : 1 / R d I R Series resistance between Input I/O PP and Output C Input capacitance per line IN Symbol Test conditions Min. Typ. Max. Unit V I = 1 mA 6 7 8 V BR R V = 3V I RM 1 A RM R 80 100 120 I/O R I = 10 A, t = 2.5 s (see note 1) 1 d pp p CIN at 0V bias 50 pF Note 1 : to calculate the ESD residual voltage, please refer to the paragraphESD PROTECTIO on pages 4 & 5 2/10