M74HC164RM13TR STMicroelectronics

M74HC164 8 BIT SIPO SHIFT REGISTER HIGH SPEED : f = 62MHz (TYP.) at V =6V MAX CC LOW POWER DISSIPATION: I =4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V =V =28% V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I =4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t PLH PHL ORDER CODES WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2V to 6V CC DIP M74HC164B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC164M1R M74HC164RM13TR 74 SERIES 164 TSSOP M74HC164TTR DESCRIPTION The M74HC164 is an high speed CMOS 8 BIT transition on the clock inputs shifts data one place SIPO SHIFT REGISTER fabricated with silicon to the right and enters into QA the logic NAND of 2 gate C MOS technology. the two data inputs (A x B), the data that existed The M74HC164 is an 8 bit shift register with serial before the rising clock edge. A low level on the data entry and an output from each of the eight clear input overrides all other inputs and clears the stages. Data is entered serially through one of two register asynchronously, forcing all Q outputs low. inputs (A or B), either of these inputs can be used All inputs are equipped with protection circuits as an active high enable for data entry through the against static discharge and transient excess other input. An unused input must be high, or both voltage. inputs connected together. Each low-to-high PIN CONNECTION AND IEC LOGIC SYMBOLS June 2003 1/13 Obsolete Product(s) - Obsolete Product(s)M74HC164 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1,2 A, B Data Inputs 3, 4, 5, 6, 10, QA to QH Outputs 11, 12, 13 Clock Input (LOW to 8 CLOCK HIGH, Edge Triggered 9 CLEAR Master Reset Input 7 GND Ground (0V) 14 Vcc Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS SERIAL IN CLEAR CLOCK QA QB ........... QH AB L X X X L L ........... L H X X NO CHANGE H L X L QAn ........... QGn H X L L QAn ........... QGn H H H H QAn ........... QGn X : Dont Care QAn - QGn : The level of QA - QG, respectively. before the most-recent transition of the clock LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/13 Obsolete Product(s) - Obsolete Product(s)