Si5415AEDU www.vishay.com Vishay Siliconix P-Channel 20 V (D-S) MOSFET FEATURES PRODUCT SUMMARY TrenchFET Power MOSFET a V (V) R ( ) (Max.) I (A) Q (Typ.) DS DS(on) D g Thermally Enhanced PowerPAK ChipFET Package 0.0096 at V = - 4.5 V - 25 GS - Small Footprint Area - 20 0.0132 at V = - 2.5 V - 25 43 nC GS - Low On-Resistance 0.0220 at V = - 1.8 V - 7 100 % R and UIS Tested GS g Typical ESD Protection: 5500 V (HBM) PowerPAK ChipFET Single Material categorization: For definitions of compliance please see www.vishay.com/doc 99912 1 2 APPLICATIONS S D 3 Portable Devices such as Smart Phones, D D 4 Tablet PCs and Mobile Computing D D 8 G - Battery Switch D 7 - Load Switch S 6 S G - Power Management 5 Marking Code Bottom View LC XXX Lot Traceability D Ordering Information: and Date Code P-Channel MOSFET Si5415AEDU-T1-GE3 (Lead (Pb)-free and Halogen-free) Part Code ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) C Parameter Symbol LimitUnit Drain-Source Voltage V - 20 DS V Gate-Source Voltage V 8 GS a T = 25 C - 25 C a T = 70 C - 25 C Continuous Drain Current (T = 150 C) I J D b, c T = 25 C - 15 A b, c T = 70 C - 12 A A Pulsed Drain Current (t = 100 s) I - 70 DM a T = 25 C - 25 C Continuous Source-Drain Diode Current I S b, c T = 25 C - 2.6 A Single Avalanche Current I - 15 AS L = 0.1 mH Single Avalanche Energy E 11 mJ AS T = 25 C 31 C T = 70 C 20 C Maximum Power Dissipation P W D b, c T = 25 C 3.1 A b, c T = 70 C 2 A Operating Junction and Storage Temperature Range T , T - 50 to 150 J stg C d, e Soldering Recommendations (Peak Temperature) 260 THERMAL RESISTANCE RATINGS Parameter Symbol TypicalMaximumUnit b, f Maximum Junction-to-Ambient t 5 s R 34 40 thJA C/W Maximum Junction-to-Case (Drain) Steady State R 34 thJC Notes a. Package limited. b. Surface mounted on 1 x 1 FR4 board. c. t = 5 s. d. See solder profile (www.vishay.com/doc 73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 90 C/W. S13-1673-Rev. A, 29-Jul-13 Document Number: 62889 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 1.9 mmSi5415AEDU www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J Parameter Symbol Test Conditions Min.Typ.Max.Unit Static Drain-Source Breakdown Voltage V V = 0 V, I = - 250 A - 20 V DS GS D V Temperature Coefficient V /T - 11 DS DS J I = - 250 A mV/C D V Temperature Coefficient V /T 2.8 GS(th) GS(th) J Gate-Source Threshold Voltage V V = V , I = - 250 A - 0.4 - 1 V GS(th) DS GS D V = 0 V, V = 8 V 2 DS GS Gate-Source Leakage I GSS V = 0 V, V = 4.5 V 0.2 DS GS A V = - 20 V, V = 0 V - 1 DS GS Zero Gate Voltage Drain Current I DSS V = - 20 V, V = 0 V, T = 55 C - 10 DS GS J a On-State Drain Current I V - 5 V, V = - 4.5 V - 10 A D(on) DS GS V = - 4.5 V, I = - 10 A 0.0081 0.0096 GS D a Drain-Source On-State Resistance R V = - 2.5 V, I = - 5 A 0.0110 0.0132 DS(on) GS D V = - 1.8 V, I = - 2 A 0.0170 0.0220 GS D a Forward Transconductance g V = - 10 V, I = - 10 A 47 S fs GS D b Dynamic Input Capacitance C 4300 iss Output Capacitance C 445V = - 10 V, V = 0 V, f = 1 MHz pF oss DS GS Reverse Transfer Capacitance C 400 rss V = - 10 V, V = - 8 V, I = - 14 A 80 120 DS GS D Total Gate Charge Q g 43 65 nC Gate-Source Charge Q 7V = - 10 V, V = - 4.5 V, I = - 14 A gs DS GS D Gate-Drain Charge Q 11.4 gd Gate Resistance R f = 1 MHz 0.6 3.3 6.6 g Turn-On Delay Time t 30 60 d(on) Rise Time t 45 90 r V = - 10 V, R = 1 DD L I - 10 A, V = - 4.5 V, R = 1 Turn-Off Delay Time t 75D GEN g 150 d(off) Fall Time t 2550 f ns Turn-On Delay Time t 12 25 d(on) Rise Time t 510 r V = - 10 V, R = 1 DD L I - 10 A, V = - 8 V, R = 1 Turn-Off Delay Time t 80D GEN g 160 d(off) Fall Time t 2040 f Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I T = 25 C - 25 S C A Pulse Diode Forward Current (t = 100 s) I - 70 SM Body Diode Voltage V I = - 10 A, V = 0 V - 0.8 - 1.2 V SD S GS Body Diode Reverse Recovery Time t 35 70 ns rr Body Diode Reverse Recovery Charge Q 21 40 nC rr I = - 10 A, dI/dt = 100 A/s, T = 25 C F J Reverse Recovery Fall Time t 20 a ns Reverse Recovery Rise Time t 15 b Notes a. Pulse test pulse width 300 s, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S13-1673-Rev. A, 29-Jul-13 Document Number: 62889 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000