Si7102DN Vishay Siliconix N-Channel 12-V (D-S) MOSFET FEATURES PRODUCT SUMMARY Halogen-free According to IEC 61249-2-21 e V (V) R () Q (Typ.) I (A) DS DS(on) g D Available 0.0038 at V = 4.5 V 35 GS TrenchFET Power MOSFET 12 41 nC 0.0047 at V = 2.5 V 35 GS Low Thermal Resistance PowerPAK Package with Small Size and Low 1.07 mm Profile 100 % R Tested g PowerPAK 1212-8 APPLICATIONS Secondary Synchronous Rectification S 3.30 mm 3.30 mm Point-of-Load 1 S D 2 Load Switch S 3 G 4 D 8 D 7 D G 6 D 5 Bottom View S Ordering Information: Si7102DN-T1-E3 (Lead (Pb)-free) Si7102DN-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS T = 25 C, unless otherwise noted A Parameter Symbol LimitUnit V Drain-Source Voltage 12 DS V V Gate-Source Voltage 8 GS e T = 25 C 35 C e T = 70 C C 35 Continuous Drain Current (T = 150 C) I J D a, b T = 25 C A 25 a, b T = 70 C A A 17.8 I Pulsed Drain Current 60 DM e T = 25 C 35 C Continuous Source-Drain Diode Current I S a, b T = 25 C A 3.2 T = 25 C 52 C T = 70 C 33 C P Maximum Power Dissipation W D a, b T = 25 C A 3.8 a, b T = 70 C A 2.4 T , T Operating Junction and Storage Temperature Range - 50 to 150 J stg C c, d 260 Soldering Recommendations (Peak Temperature) Notes: a. Surface Mounted on 1 x 1 FR4 board. b. t = 10 s. c. See Solder Profile (www.vishay.com/ppg 73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. d. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. e. Package limited. Document Number: 74250 www.vishay.com S-83044-Rev. B, 22-Dec-08 1 Si7102DN Vishay Siliconix THERMAL RESISTANCE RATINGS Parameter Symbol TypicalMaximumUnit a, b R t 10 s 24 33 Maximum Junction-to-Ambient thJA C/W Maximum Junction-to-Case (Drain) Steady State R 1.9 2.4 thJC Notes: a. Surface Mounted on 1 x 1 FR4 board. b. Maximum under Steady State conditions is 81 C/W. SPECIFICATIONS T = 25 C, unless otherwise noted J Parameter Symbol Test Conditions Min.Typ.Max.Unit Static V V = 0 V, I = 250 A Drain-Source Breakdown Voltage 12 V DS GS D V Temperature Coefficient V /T 12 DS DS J I = 250 A mV/C D V Temperature Coefficient V /T - 3.1 GS(th) GS(th) J Gate-Source Threshold Voltage V V = V , I = 250 A 0.4 1.0 V GS(th) DS GS D I V = 0 V, V = 8 V Gate-Source Leakage 100 nA GSS DS GS V = 12 V, V = 0 V 1 DS GS I Zero Gate Voltage Drain Current A DSS V = 12 V, V = 0 V, T = 55 C 10 DS GS J a I V 5 V, V = 4.5 V 30 A On-State Drain Current D(on) DS GS V = 4.5 V, I = 15 A 0.0031 0.0038 GS D a R Drain-Source On-State Resistance DS(on) V = 2.5 V, I = 10 A 0.0037 0.0047 GS D a g V = 5 V, I = 15 A 110 S Forward Transconductance fs DS D b Dynamic Input Capacitance C 3720 iss C V = 6 V, V = 0 V, f = 1 MHz Output Capacitance 1290 pF oss DS GS Reverse Transfer Capacitance C 840 rss V = 6 V, V = 8 V, I = 10 A 73 110 DS GS D Q Total Gate Charge g 41 62 nC Gate-Source Charge Q V = 6 V, V = 4.5 V, I = 10 A 4.5 gs DS GS D Q Gate-Drain Charge 8.5 gd Gate Resistance R f = 1 MHz 1.4 2.1 g t Turn-On Delay Time 27 41 d(on) t Rise Time V = 6 V, R = 1.2 125 190 r DD L I 5 A, V = 4.5 V, R = 1 t Turn-Off Delay Time D GEN g 53 80 d(off) t Fall Time 12 18 f ns t Turn-On Delay Time 16 25 d(on) t Rise Time V = 6 V, R = 1.2 55 85 r DD L I 5 A, V = 8 V, R = 1 t Turn-Off Delay Time D GEN g 53 80 d(off) t Fall Time 915 f www.vishay.com Document Number: 74250 2 S-83044-Rev. B, 22-Dec-08