SiE808DF Vishay Siliconix N-Channel 20-V (D-S) MOSFET FEATURES PRODUCT SUMMARY Halogen-free According to IEC 61249-2-21 a I (A) D Definition TrenchFET Gen II Power MOSFET Silicon Package e V (V) R () Q (Typ.) Limit Limit Ultra Low Thermal Resistance Using Top- DS DS(on) g Exposed PolarPAK Package for Double- 0.0016 at V = 10 V 220 60 GS Sided Cooling 20 46 nC 0.0025 at V = 4.5 V 117 60 Leadframe-Based New Encapsulated Package GS - Die Not Exposed Package Drawing - Same Layout Regardless of Die Size www.vishay.com/doc 72945 Low Q /Q Ratio Helps Prevent Shoot-Through gd gs 100 % R and UIS Tested PolarPAK g Compliant to RoHS directive 2002/95/EC 10 9 8 7 6 D G S S D 67 89 10 APPLICATIONS VRM D DC/DC Conversion: Low-Side Synchronous Rectification D DS G D G D G S S D 5 432 1 1 2 3 4 5 S Top View Bottom View Top surface is connected to pins 1, 5, 6, and 10 N-Channel MOSFET For Related Documents Ordering Information: SiE808DF-T1-E3 (Lead (Pb)-free) www.vishay.com/ppg 73739 SiE808DF-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS T = 25 C, unless otherwise noted A Parameter Symbol Limit Unit Drain-Source Voltage V 20 DS V Gate-Source Voltage V 20 GS 220 (Silicon Limit) T = 25 C C a 60 (Package Limit) a Continuous Drain Current (T = 150 C) I T = 70 C J D 60 C b, c T = 25 C 45 A b, c A T = 70 C 36 A Pulsed Drain Current I 100 DM a T = 25 C 60 C Continuous Source-Drain Diode Current I b, c S T = 25 C 4.3 A Single Pulse Avalanche Current I 35 AS L = 0.1 mH Avalanche Energy E 61 mJ AS T = 25 C 125 C T = 70 C 80 C P Maximum Power Dissipation W D b, c T = 25 C 5.2 A b, c T = 70 C 3.3 A T , T Operating Junction and Storage Temperature Range - 55 to 150 J stg C d, e 260 Soldering Recommendations (Peak Temperature) Notes: a. Package limited is 60 A. b. Surface Mounted on 1 x 1 FR4 board. c. t = 10 s. d. See Solder Profile (www.vishay.com/doc 73257). The PolarPAK is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. Document Number: 73739 www.vishay.com S09-1337-Rev. B, 13-Jul-09 1SiE808DF Vishay Siliconix THERMAL RESISTANCE RATINGS Parameter Symbol TypicalMaximumUnit a, b t 10 s R 20 24 Maximum Junction-to-Ambient thJA Maximum Junction-to-Case (Drain Top) R (Drain) 0.8 1 C/W thJC Steady State a, c R (Source) 2.2 2.7 Maximum Junction-to-Case (Source) thJC Notes: a. Surface Mounted on 1 x 1 FR4 board. b. Maximum under Steady State conditions is 68 C/W. c. Measured at source pin (on the side of the package). SPECIFICATIONS T = 25 C, unless otherwise noted J Parameter Symbol Test Conditions Min.Typ.Max.Unit Static V = 0 V, I = 250 A Drain-Source Breakdown Voltage V 20 V GS D DS V Temperature Coefficient V /T 26.5 DS DS J I = 250 A mV/C D V Temperature Coefficient V /T - 7.3 GS(th) GS(th) J V = V , I = 250 A Gate-Source Threshold Voltage V 1.5 2.3 3 V DS GS D GS(th) V = 0 V, V = 20 V Gate-Source Leakage I 100 nA DS GS GSS V = 20 V, V = 0 V 1 DS GS I Zero Gate Voltage Drain Current A DSS V = 20 V, V = 0 V, T = 55 C 10 DS GS J a I V 5 V, V = 10 V 25 A On-State Drain Current D(on) DS GS V = 10 V, I = 25 A 0.0013 0.0016 GS D a R Drain-Source On-State Resistance DS(on) V = 4.5 V, I = 25 A 0.0021 0.0025 GS D a Forward Transconductance g V = 10 V, I = 25 A 95 S fs DS D b Dynamic C Input Capacitance 8800 iss C V = 10 V, V = 0 V, f = 1 MHz Output Capacitance 1600 pF oss DS GS C Reverse Transfer Capacitance 600 rss V = 10 V, V = 10 V, I = 25 A 102 155 DS GS D Q Total Gate Charge g 46 70 nC Q V = 10 V, V = 4.5 V, I = 20 A Gate-Source Charge 26 gs DS GS D Q Gate-Drain Charge 8 gd R Gate Resistance f = 1 MHz 0.9 1.35 g t Turn-On Delay Time 180 270 d(on) t V = 10 V, R = 1 Rise Time 215 325 r DD L t I 10 A, V = 4.5 V, R = 1 Turn-Off Delay Time 50 75 d(off) D GEN g t Fall Time 15 25 f ns t Turn-On Delay Time 25 40 d(on) t V = 10 V, R = 1 Rise Time 55 85 r DD L t I 10 A, V = 10 V, R = 1 Turn-Off Delay Time 55 85 d(off) D GEN g t Fall Time 10 15 f Drain-Source Body Diode Characteristics I T = 25 C Continuous Source-Drain Diode Current 60 S C A a I Pulse Diode Forward Current 100 SM V I = 10 A Body Diode Voltage 0.8 1.2 V SD S t Body Diode Reverse Recovery Time 56 85ns rr Q Body Diode Reverse Recovery Charge 60 90 nC rr I = 10 A, dI/dt = 100 A/s, T = 25 C F J t Reverse Recovery Fall Time 26 a ns t Reverse Recovery Rise Time 30 b Notes: a. Pulse test pulse width 300 s, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com Document Number: 73739 2 S09-1337-Rev. B, 13-Jul-09