SiE812DF Vishay Siliconix N-Channel 40-V (D-S) MOSFET FEATURES PRODUCT SUMMARY Halogen-free According to IEC 61249-2-21 a I (A) D Definition TrenchFET Gen II Power MOSFET Silicon Package e V (V) R () Q (Typ.) Ultra Low Thermal Resistance Using Top- Limit Limit DS DS(on) g Exposed PolarPAK Package for Double-Sided 0.0026 at V = 10 V 163 60 GS Cooling 40 52 nC Leadframe-Based New Encapsulated Package 0.0034 at V = 4.5 V 143 60 GS - Die Not Exposed - Same Layout Regardless of Die Size Package Drawing www.vishay.com/doc 72945 Low Q /Q Ratio Helps Prevent Shoot-Through gd gs 100 % R and UIS Tested g PolarPAK Compliant to RoHS directive 2002/95/EC 10 9 8 7 6 D G S S D 67 89 10 APPLICATIONS VRM DC/DC Conversion: Low-Side Synchronous Rectification D D DS G D G D G S S D 5 432 1 1 2 3 4 5 Top View Bottom View Top surface is connected to pins 1, 5, 6, and 10 S N-Channel MOSFET Ordering Information: SiE812DF-T1-E3 (Lead (Pb)-free) For Related Documents SiE812DF-T1-GE3 (Lead (Pb)-free and Halogen-free) www.vishay.com/ppg 74337 ABSOLUTE MAXIMUM RATINGS T = 25 C, unless otherwise noted A Parameter Symbol Limit Unit V Drain-Source Voltage 40 DS V Gate-Source Voltage V 20 GS 163 (Silicon Limit) T = 25 C C a 60 (Package Limit) a Continuous Drain Current (T = 150 C) T = 70 C I J C D 60 b, c T = 25 C A 33 b, c T = 70 C A A 27 Pulsed Drain Current I 100 DM a T = 25 C 60 C Continuous Source-Drain Diode Current I b, c S T = 25 C 4.3 A Single Pulse Avalanche Current I 50 AS L = 0.1 mH Avalanche Energy E 125 mJ AS T = 25 C 125 C T = 70 C 80 C P Maximum Power Dissipation W D b, c T = 25 C A 5.2 b, c T = 70 C A 3.3 T , T Operating Junction and Storage Temperature Range - 55 to 150 J stg C d, e 260 Soldering Recommendations (Peak Temperature) Notes: a. Package limited. b. Surface Mounted on 1 x 1 FR4 board. c. t = 10 s. d. See Solder Profile (www.vishay.com/doc 73257). The PolarPAK is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. Document Number: 74337 www.vishay.com S09-1337-Rev. B, 13-Jul-09 1SiE812DF Vishay Siliconix THERMAL RESISTANCE RATINGS Parameter Symbol TypicalMaximumUnit a, b R Maximum Junction-to-Ambient t 10 s 20 24 thJA R (Drain) Maximum Junction-to-Case (Drain Top) 0.8 1 C/W thJC Steady State a, c R (Source) 2.2 2.7 Maximum Junction-to-Case (Source) thJC Notes: a. Surface Mounted on 1 x 1 FR4 board. b. Maximum under Steady State conditions is 68 C/W. c. Measured at source pin (on the side of the package). SPECIFICATIONS T = 25 C, unless otherwise noted J Parameter Symbol Test Conditions Min.Typ.Max.Unit Static V = 0 V, I = 250 A Drain-Source Breakdown Voltage V 40 V GS D DS V Temperature Coefficient V /T 45.5 DS DS J I = 250 A mV/C D V Temperature Coefficient V /T - 7.1 GS(th) GS(th) J V V = V , I = 250 A Gate-Source Threshold Voltage 1.5 2.3 3 V GS(th) DS GS D I V = 0 V, V = 20 V Gate-Source Leakage 100 nA GSS DS GS V = 40 V, V = 0 V 1 DS GS I Zero Gate Voltage Drain Current A DSS V = 40 V, V = 0 V, T = 55 C 10 DS GS J a I V 5 V, V = 10 V On-State Drain Current 25 A D(on) DS GS V = 10 V, I = 25 A 0.0022 0.0026 GS D a R Drain-Source On-State Resistance DS(on) V = 4.5 V, I = 25 A 0.0028 0.0034 GS D a g V = 20 V, I = 25 A Forward Transconductance 154 S fs DS D b Dynamic C Input Capacitance 8300 iss C V = 20 V, V = 0 V, f = 1 MHz pF Output Capacitance 800 oss DS GS C Reverse Transfer Capacitance 360 rss V = 20 V, V = 10 V, I = 25 A 111 170 DS GS D Total Gate Charge Q g 52 80 nC Q V = 10 V, V = 4.5 V, I = 20 A Gate-Source Charge 25 gs DS GS D Q Gate-Drain Charge 15 gd R Gate Resistance f = 1 MHz 1.15 1.7 g t Turn-On Delay Time 50 75 d(on) t V = 20 V, R = 2 Rise Time 265 400 r DD L t I 10 A, V = 4.5 V, R = 1 Turn-Off Delay Time 50 75 d(off) D GEN g t Fall Time 10 15 f ns t Turn-On Delay Time 20 30 d(on) t Rise Time V = 20 V, R = 2 15 25 r DD L t I 10 A, V = 10 V, R = 1 Turn-Off Delay Time 60 90 d(off) D GEN g t Fall Time 10 15 f Drain-Source Body Diode Characteristics I T = 25 C Continuous Source-Drain Diode Current 60 S C A a I Pulse Diode Forward Current 100 SM V I = 10 A Body Diode Voltage 0.8 1.2 V SD S t Body Diode Reverse Recovery Time 50 75 ns rr Q Body Diode Reverse Recovery Charge 65 100 nC rr I = 10 A, dI/dt = 100 A/s, T = 25 C F J t Reverse Recovery Fall Time 27 a ns t 23 Reverse Recovery Rise Time b Notes: a. Pulse test pulse width 300 s, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com Document Number: 74337 2 S09-1337-Rev. B, 13-Jul-09