Si7463DP www.vishay.com Vishay Siliconix P-Channel 40 V (D-S) MOSFET FEATURES PRODUCT SUMMARY TrenchFET Power MOSFETs V (V) R ( )I (A) DS DS(on) D New low thermal resistance PowerPAK 0.0092 at V = -10 V -18.6 GS package with low 1.07 mm profile -40 0.0140 at V = -4.5 V -15 GS Material categorization: For definitions of compliance please see PowerP AK SO-8 www.vishay.com/doc 99912 Available S S 6.15 mm 5.15 mm 1 S 2 S 3 G 4 G D 8 D 7 D 6 D 5 Bottom View D Ordering Information: Si7463DP-T1-E3 (Lead (Pb)-free) Si7463DP-T1-GE3 (Lead (Pb)-free and Halogen-free) P-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL 10 s STEADY STATE UNIT Drain-Source Voltage V -40 DS V Gate-Source Voltage V 20 GS T = 25 C -18.6 -11 A a Continuous Drain Current (T = 150 C) I J D T = 70 C -15 -8.9 A A Pulsed Drain Current I -60 DM a Continuous Source Current (Diode Conduction) I -4.5 -1.6 S T = 25 C 5.4 1.9 A a Maximum Power Dissipation P W D T = 70 C 3.4 1.2 A Operating Junction and Storage Temperature Range T , T -55 to 150 J stg C b, c Soldering Recommendations (Peak Temperature) 260 THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYPICAL MAXIMUM UNIT t 10 s 18 23 a Maximum Junction-to-Ambient R thJA Steady State 52 65 C/W Maximum Junction-to-Case (Drain) Steady State R 11.3 thJC Notes a. Surface mounted on 1 x 1 FR4 board. b. See solder profile (www.vishay.com/ppg 73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. c. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. S13-2282-Rev. G, 04-Nov-13 Document Number: 72440 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 Si7463DP www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Gate Threshold Voltage V V = V , I = -250 A -1 - -3 V GS(th) DS GS D Gate-Body Leakage I V = 0 V, V = 20 V - - 100 nA GSS DS GS V = -40 V, V = 0 V - - -1 DS GS Zero Gate Voltage Drain Current I A DSS V = -40 V, V = 0 V, T = 70 C - - -10 DS GS J a On-State Drain Current I V -5 V, V = -10 V -40 - - A D(on) DS GS V = -10 V, I = -18.6 A - 0.0075 0.0092 GS D a Drain-Source On-State Resistance R DS(on) V = -4.5 V, I = -15 A - 0.0110 0.0140 GS D a Forward Transconductance g V = -15 V, I = -18.6 A - 50 - S fs DS D a Diode Forward Voltage V I = -4.5 A, V = 0 V - -0.8 -1.2 V SD S GS b Dynamic Total Gate Charge Q - 121 140 g Gate-Source Charge Q V = -20 V, V = -10 V, I = -18.6 A - 19.2 - nC gs DS GS D Gate-Drain Charge Q -30.3- gd Gate Resistance R -2.7 - g Turn-On Delay Time t -20 30 d(on) Rise Time t -25 40 r V = -20 V, R = 20 DD L I -1 A, V = -10 V, R = 6 D GEN g Turn-Off Delay Time t -200300 ns d(off) Fall Time t - 100 150 f Source-Drain Reverse Recovery Time t I = -4.5 A, dI/dt = 100 A/s - 45 70 rr F Notes a. Pulse test pulse width 300 s, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S13-2282-Rev. G, 04-Nov-13 Document Number: 72440 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000