SiR172ADP Vishay Siliconix N-Channel 30 V (D-S) MOSFET FEATURES PRODUCT SUMMARY TrenchFET Power MOSFET a, g V (V) R ( ) Max. Q (Typ.) I (A) DS DS(on) g Low Thermal Resistance PowerPAK Package D with Low 1.07 mm Profile 0.0085 at V = 10 V 24 GS 30 12.8 nC Optimized for High-Side Synchronous Rectifier 0.0105 at V = 4.5 V 24 GS Operation 100 % R and UIS Tested g PowerPAK SO-8 Material categorization: For definitions of compliance please see www.vishay.com/doc 99912 S APPLICATIONS 6.15 mm 5.15 mm 1 D S Notebook CPU Core 2 S 3 - High-Side Switch G 4 D 8 D 7 G D 6 D 5 Bottom View S Ordering Information: N-Channel MOSFET SiR172ADP-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A Parameter Symbol LimitUnit Drain-Source Voltage V 30 DS V Gate-Source Voltage V 20 GS g T = 25 C C 24 g T = 70 C C 24 Continuous Drain Current (T = 150 C) I J D b, c T = 25 C A 16.1 b, c T = 70 C A 12.9 A Pulsed Drain Current (t = 300 s) I 60 DM g T = 25 C C 24 I Continuous Source-Drain Diode Current S b, c T = 25 C A 3.5 I Single Pulse Avalanche Current 10 AS L = 0.1 mH E Avalanche Energy 5mJ AS T = 25 C 29.8 C T = 70 C 19 C P Maximum Power Dissipation W D b, c T = 25 C A 3.9 b, c T = 70 C 2.5 A T , T Operating Junction and Storage Temperature Range - 55 to 150 J stg C d, e 260 Soldering Recommendations (Peak Temperature) THERMAL RESISTANCE RATINGS Parameter Symbol TypicalMaximumUnit b, f R t 10 s 27 32 Maximum Junction-to-Ambient thJA C/W Maximum Junction-to-Case (Drain) Steady State R 3.5 4.2 thJC Notes: a. Base on T = 25 C. C b. Surface mounted on 1 x 1 FR4 board. c. t = 10 s. d. See Solder Profile (www.vishay.com/doc 73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 70 C/W. g. Package limited. Document Number: 62609 For technical questions, contact: pmostechsupport vishay.com www.vishay.com S12-2052-Rev.B, 27-Aug-12 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000SiR172ADP Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J Parameter Symbol Test Conditions Min.Typ.Max.Unit Static V V = 0 V, I = 250 A Drain-Source Breakdown Voltage 30 V DS GS D V /T V Temperature Coefficient 28 DS J DS I = 250 A mV/C D V /T V Temperature Coefficient - 4.5 GS(th) J GS(th) V V = V , I = 250 A Gate-Source Threshold Voltage 1.2 2.4 V GS(th) DS GS D I V = 0 V, V = 20 V Gate-Source Leakage 100 nA GSS DS GS V = 30 V, V = 0 V 1 DS GS I Zero Gate Voltage Drain Current A DSS V = 30 V, V = 0 V, T = 55 C 10 DS GS J a On-State Drain Current I V 5 V, V = 10 V 20 A D(on) DS GS V = 10 V, I = 10 A 0.0070 0.0085 GS D a R Drain-Source On-State Resistance DS(on) V = 4.5 V, I = 7 A 0.0085 0.0105 GS D a g V = 15 V, I = 10 A Forward Transconductance 60 S fs DS D b Dynamic Input Capacitance C 1515 iss C V = 15 V, V = 0 V, f = 1 MHz Output Capacitance 202 pF oss DS GS Reverse Transfer Capacitance C 142 rss V = 15 V, V = 10 V, I = 10 A 29 44 DS GS D Q Total Gate Charge g 12.8 20 nC Q Gate-Source Charge V = 15 V, V = 4.5 V, I = 10 A 3.8 gs DS GS D Q Gate-Drain Charge 4.1 gd R Gate Resistance f = 1 MHz 0.2 1.2 2.4 g t Turn-On Delay Time 18 36 d(on) t Rise Time V = 15 V, R = 1.5 23 45 r DD L I 10 A, V = 4.5 V, R = 1 Turn-Off Delay Time t 22 45 D GEN g d(off) t Fall Time 11 22 f ns Turn-On Delay Time t 12 24 d(on) t Rise Time V = 15 V, R = 1.5 14 28 r DD L I 10 A, V = 10 V, R = 1 Turn-Off Delay Time t 22 44 D GEN g d(off) t Fall Time 816 f Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I T = 25 C 24 S C A a I Pulse Diode Forward Current 60 SM Body Diode Voltage V I = 5 A 0.75 1.1 V SD S t Body Diode Reverse Recovery Time 15 30 ns rr Q Body Diode Reverse Recovery Charge 714 nC rr I = 5 A, dI/dt = 100 A/s, T = 25 C F J t Reverse Recovery Fall Time 8 a ns t Reverse Recovery Rise Time 7 b Notes: a. Pulse test pulse width 300 s, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com For technical questions, contact: pmostechsupport vishay.com Document Number: 62609 2 S12-2052-Rev.B, 27-Aug-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000