Product Technical OrOrdderer Folder Support NowNow InterFET IFN5197-8-9 IFN5197, IFN5198, IFN5199 Dual Matched N-Channel JFET Features TO-71 Bottom View Source InterFET N0016H Geometry 5 Drain Low Leakage: 10 pA Typical 6 Low Input Capacitance: 3.5 pF Typical Gate 3 7 Gate High Input Impedance Replacement for IFN5197,8,9 2 Drain RoHS Compliant 1 Source SMT, TH, and Bare Die Package options. SOIC8 Top View Applications Low Noise Differential Amplifier Gate 1 8 Gate Differential Amplifier Drain 2 7 Source JFET Input Op-Amps Source 3 6 Drain Description Gate 4 5 Gate The -50V InterFET IFN5197, IFN5198, and IFN5199 JFETs are targeted for low noise differential amplifier designs. Gate leakages are less than 10pA at room temperatures. The TO-71 package is hermetically sealed and suitable for military applications. Custom specifications, matching, and packaging options are available. Product Summary Parameters IFN5197 Min IFN5198 Min IFN5199 Min Unit BV Gate to Source Breakdown Voltage -50 -50 -50 V GSS IDSS Drain to Source Saturation Current 0.7 0.7 0.7 mA VGS(off) Gate to Source Cutoff Voltage -0.7 -0.7 -0.7 V G Forward Transconductance 0.7 0.7 0.7 mS FS Ordering Information Custom Part and Binning Options Available Part Number Description Case Packaging IFN5197 IFN5198 IFN5199 Through-Hole TO-71 Bulk SMP5197 SMP5198 SMP5199 Surface Mount SOIC8 Bulk 7 Tape and Reel: Max 500 Pieces Minimum 500 Pieces SMP5197 SMP5198 SMP5199 13 Tape and Reel: Max 2,500 Pieces SOIC8 Tape and Reel IFN5197COT IFN5198COT IFN5199COT * Chip Orientated Tray (COT Waffle Pack) COT 70/Waffle Pack IFN5197CFT IFN5198CFT IFN5199CFT * Chip Face-up Tray (CFT Waffle Pack) CFT 70/Waffle Pack * Bare die packaged options are designed for matched specifications but not 100% tested Disclaimer: It is the Buyers responsibility for designing, validating and testing the end application under all field use cases and extreme use conditions. Guaranteeing the application meets required standards, regulatory compliance, and all safety and security requirements is the responsibility of the Buyer. These resources are subject to change without notice. IF35100.R00Product Technical OrOrdderer Folder Support NowNow InterFET IFN5197-8-9 Electrical Characteristics Maximum Ratings ( TA = 25C, Unless otherwise specified) Parameters Value Unit VRGS Reverse Gate Source and Gate Drain Voltage -50 V I Continuous Forward Gate Current 50 mA FG P Continuous Device Power Dissipation 250 mW D P Power Derating 4.3 mW/C T Operating Junction Temperature -55 to 125 C J T Storage Temperature -65 to 150 C STG Static Characteristics ( TA = 25C, Unless otherwise specified) IFN5197, IFN5198, IFN5199 Parameters Conditions Min Typ Max Unit Gate to Source V I = -1A,V = 0V -50 V (BR)GSS G DS Breakdown Voltage Gate to Source VGS = -30V, VDS = 0V, TA = 25C -25 pA I GSS Reverse Current VGS = -30V, VDS = 0V, TA = 150C -50 nA VDS = 20V, ID = 200A, TA = 25C -15 pA I Gate Operating Current G VDS = 20V, ID = 200A, TA = 125C -15 nA Gate to Source V V = 20V, I = 1nA -0.7 -4.0 V GS(OFF) DS D Cutoff Voltage V Gate Source Voltage V = 20V, I = 200A -0.2 -3.8 V GS DS D Drain to Source V = 20V, V = 0V DS GS I 0.7 7 mA DSS Saturation Current (Pulsed) Dynamic Characteristics ( TA = 25C, Unless otherwise specified) IFN5197, IFN5198, IFN5199 Parameters Conditions Min Typ Max Unit Forward V = 20V, V = 0V, f = 1kHz 1 4 DS GS GFS mS Transconductance V = 20V, I = 200A, f = 1kHz 0.7 1.6 DS D V = 20V, V = 0V, f = 1kHz 50 DS GS GOS Output Conductance S V = 20V, I = 200A, f = 1kHz 4 DS D Ciss Input Capacitance VDS = 20V, VGS = 0V, f = 1MHz 6 pF C Reverse Capacitance V = 20V, V = 0V, f = 1MHz 2 pF rss DS GS Equivalent Circuit V = 20V, I = 200A, f = 1kHz 20 e DS D nV/ Hz n Input Noise Voltage IFN5197 5 Differential Gate V V GS1 GS2 VDS = 20V, ID = -200A IFN5198 10 mV Source Voltage IFN5199 15 Differential Gate IFN5197 1 V V VDS = 20V, ID = 200A GS1 GS2 Source Voltage with IFN5198 2.5 mV/C T TA = 25C, TB = 125C Temperature IFN5199 4 IFN5197-8-9 2 of 4 InterFET Corporation Document Number: IF35100.R00 www.InterFET.com December, 2018