Document Number: MD7IC2012N Freescale Semiconductor Rev. 0, 4/2013 Technical Data RF LDMOS Wideband Integrated MD7IC2012NR1 Power Amplifiers MD7IC2012GNR1 The MD7IC2012N wideband integrated circuit is designed with onchip matching that makes it usable from 1805 to 2170 MHz. This multistage structure is rated for 24 to 32 volt operation and covers all typical cellular base station modulation formats. 18052170 MHz, 1.3 W AVG., 28 V Driver Application 2100 MHz SINGLE WCDMA RF LDMOS WIDEBAND Typical SingleCarrier WCDMA Performance: V = 28 Volts, DD INTEGRATED POWER AMPLIFIERS I =I = 20 mA, I =I = 70 mA, P = 1.3 Watts Avg., DQ1A DQ1B DQ2A DQ2B out IQ Magnitude Clipping, Channel Bandwidth = 3.84 MHz, Input Signal PAR = 7.5 dB 0.01% Probability on CCDF. G PAE ACPR TO270 WB14 ps Frequency (dB) (%) (dBc) PLASTIC MD7IC2012NR1 2110 MHz 31.0 14.7 51.3 2140 MHz 31.3 14.8 51.2 2170 MHz 31.5 14.9 50.6 TO270 WB14 GULL Capable of Handling 5:1 VSWR, 32 Vdc, 2140 MHz, 14 Watts CW PLASTIC Output Power (3 dB Input Overdrive from Rated P ) out MD7IC2012GNR1 Typical P 1 dB Compression Point 12 Watts CW out Driver Application 1800 MHz Typical SingleCarrier WCDMA Performance: V = 28 Volts, DD I =I = 20 mA, I =I = 70 mA, P = 1.3 Watts Avg., DQ1A DQ1B DQ2A DQ2B out IQ Magnitude Clipping, Channel Bandwidth = 3.84 MHz, Input Signal PAR = 7.5 dB 0.01% Probability on CCDF. G PAE ACPR ps Frequency (dB) (%) (dBc) 1805 MHz 32.8 13.4 51.0 1840 MHz 32.2 13.6 51.2 1880 MHz 31.6 13.8 51.8 Features Characterized with Series Equivalent LargeSignal Impedance Parameters and Common Source SParameters OnChip Matching (50 Ohm Input, DC Blocked) (1) Integrated Quiescent Current Temperature Compensation with Enable/Disable Function Integrated ESD Protection Designed for Digital Predistortion Error Correction Systems Optimized for Doherty Applications 225C Capable Plastic Package In Tape and Reel. R1 Suffix = 500 Units, 44 mm Tape Width, 13inch Reel. 1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to V DS1A V 1 DS1A V 2 GS2A RF RF /V inA out1 DS2A 14 V 3 GS1A RF /V out1 DS2A RF 4 inA N.C. 5 V N.C. 6 GS1A Quiescent Current N.C. 7 (1) V Temperature Compensation GS2A N.C. 8 RF 9 13 RF /V inB out2 DS2B V GS1B Quiescent Current V 10 GS1B (1) V Temperature Compensation V 11 GS2B GS2B V 12 DS1B (Top View) RF inB RF /V out2 DS2B Note: Exposed backside of the package is V the source terminal for the transistors. DS1B Figure 1. Functional Block Diagram Figure 2. Pin Connections Table 1. Maximum Ratings Rating Symbol Value Unit DrainSource Voltage V 0.5, +65 Vdc DSS GateSource Voltage V 0.5, +10 Vdc GS Operating Voltage V 32, +0 Vdc DD Storage Temperature Range T 65 to +150 C stg Case Operating Temperature T 150 C C (2,3) Operating Junction Temperature T 225 C J Input Power P 20 dBm in Table 2. Thermal Characteristics (3,4) Characteristic Symbol Value Unit Thermal Resistance, Junction to Case R C/W JC Case Temperature 77C, 1.3 W, 2170 MHz Stage 1, 28 Vdc, I = I = 20 mA, 2170 MHz 7.8 DQ1A DQ1B Stage 2, 28 Vdc, I = I = 70 mA, 2170 MHz 3.1 DQ2A DQ2B Case Temperature 79C, 12 W CW, 2170 MHz Stage 1, 28 Vdc, I = I = 20 mA, 2170 MHz 7.3 DQ1A DQ1B Stage 2, 28 Vdc, I = I = 70 mA, 2170 MHz 2.4 DQ2A DQ2B Table 3. ESD Protection Characteristics Test Methodology Class Human Body Model (per JESD22A114) 1A Machine Model (per EIA/JESD22A115) A Charge Device Model (per JESD22C101) II Table 4. Moisture Sensitivity Level Test Methodology Rating Package Peak Temperature Unit Per JESD22A113, IPC/JEDEC JSTD020 3 260 C 1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to