DocumentNumber:MD7IC21100N Freescale Semiconductor Rev. 2, 2/2012 Technical Data RFLDMOSWidebandIntegrated MD7IC21100NR1 PowerAmplifiers MD7IC21100GNR1 The MD7IC21100N wideband integrated circuit is designed with on--chip matching that makes it usable from 2110 to 2170 MHz. This multi--stage MD7IC21100NBR1 structureisratedfor24to32Voltoperationandcoversalltypicalcellularbase station modulation formats including TD--SCDMA. TypicalSingle--Carrier W--CDMA Performance: V =28Volts,I + DD DQ1A I = 190mA, I +I = 925mA, P = 32Watts Avg., 2110--2170MHz,32WAVG.,28V DQ1B DQ2A DQ2B out f = 2167.5MHz, IQ MagnitudeClipping, ChannelBandwidth= 3.84MHz, SINGLEW--CDMA Input SignalPAR = 7.5dB 0.01%Probability onCCDF. RFLDMOSWIDEBAND Power Gain 28.5dB INTEGRATEDPOWERAMPLIFIERS Power AddedEfficiency 30% DeviceOutput SignalPAR 6.1dB 0.01%Probability onCCDF ACPR 5MHz Offset --38dBc in3.84MHz ChannelBandwidth CASE1618--02 Capableof Handling5:1VSWR, 32Vdc, 2140MHz, P = 110Watts CW out TO--270WB--14 (3dB Input Overdrivefrom RatedP ) out PLASTIC Stableintoa5:1VSWR. AllSpurs Below --60dBc 1mW to100Watts CW MD7IC21100NR1 P . out Typical P 1dB CompressionPoint110Watts CW out CASE1621--02 Features TO--270WB--14GULL 100%PAR Testedfor GuaranteedOutput Power Capability PLASTIC MD7IC21100GNR1 CharacterizedwithSeries Equivalent Large--SignalImpedanceParameters andCommonSourceS-Parameters On--ChipMatching(50Ohm Input, onaper sidebasis, DC Blocked) CASE1617--02 Internally Matchedfor Easeof Use TO--272WB--14 IntegratedQuiescent Current TemperatureCompensationwith PLASTIC (1) Enable/DisableFunction MD7IC21100NBR1 IntegratedESD Protection 225C CapablePlastic Package InTapeandReel. R1Suffix = 500Units, 44mm TapeWidth, 13inchReel. V DS1A V 1 DS1A V 2 GS2A RF RF /V 14 inA V 3 out1 DS2A GS1A RF /V out1 DS2A NC 4 RF 5 inA NC 6 V GS1A QuiescentCurrent NC 7 (1) V TemperatureCompensation GS2A RF 8 inB NC 9 13 RF /V out2 DS2B V GS1B QuiescentCurrent V 10 GS1B (1) V TemperatureCompensation GS2B V 11 GS2B V 12 DS1B RF (TopView) inB RF /V out2 DS2B Note: Exposed backside of the package is V DS1B thesourceterminalforthetransistors. Figure1.FunctionalBlockDiagram Figure2.PinConnections 1. RefertoAN1977,QuiescentCurrentThermalTrackingCircuitintheRFIntegratedCircuitFamilyandtoAN1987,QuiescentCurrentControl fortheRFIntegratedCircuitDeviceFamily.GotoTable1.MaximumRatings Rating Symbol Value Unit Drain--SourceVoltage V --0.5,+65 Vdc DSS Gate--SourceVoltage V --0.5,+6.0 Vdc GS OperatingVoltage V 32,+0 Vdc DD StorageTemperatureRange T --65to+150 C stg CaseOperatingTemperature T 150 C C (1,2) OperatingJunctionTemperature T 225 C J InputPower P 29 dBm in Table2.ThermalCharacteristics (2,3) Characteristic Symbol Value Unit ThermalResistance,JunctiontoCase R C/W JC (CaseTemperature76C,32W CW) Stage1,28Vdc,I +I =190mA 2.7 DQ1A DQ1B (CaseTemperature76C,32W CW) Stage2,28Vdc,I +I =925mA 0.7 DQ2A DQ2B Table3.ESDProtectionCharacteristics TestMethodology Class HumanBody Model(perJESD22--A114) 0 MachineModel(perEIA/JESD22--A115) A ChargeDeviceModel(perJESD22--C101) III Table4.MoistureSensitivityLevel TestMethodology Rating PackagePeakTemperature Unit PerJESD22--A113,IPC/JEDECJ--STD--020 3 260 C Table5.ElectricalCharacteristics (T =25Cunless otherwisenoted) A Characteristic Symbol Min Typ Max Unit (4) Stage1OffCharacteristics ZeroGateVoltageDrainLeakageCurrent I 10 Adc DSS (V =65Vdc,V =0Vdc) DS GS ZeroGateVoltageDrainLeakageCurrent I 1 Adc DSS (V =28Vdc,V =0Vdc) DS GS Gate--SourceLeakageCurrent I 1 Adc GSS (V =1.5Vdc,V =0Vdc) GS DS (4) Stage1OnCharacteristics GateThresholdVoltage V 1 2 3 Vdc GS(th) (V =10Vdc,I =50Adc) DS D GateQuiescentVoltage V 2.9 Vdc GS(Q) (V =28Vdc,I +I =190mAdc) DS DQ1A DQ1B FixtureGateQuiescentVoltage V 5.5 6.3 7 Vdc GG(Q) (V =28Vdc,I +I =190mAdc,MeasuredinFunctionalTest) DD DQ1A DQ1B 1. Continuous useatmaximum temperaturewillaffectMTTF. 2. MTTFcalculatoravailableat