74F112 Dual JK Negative Edge-Triggered Flip-Flop
April 1988
Revised September 2000
74F112
Dual JK Negative Edge-Triggered Flip-Flop
Simultaneous LOW signals on S and C force both Q and
D D
General Description
Q HIGH.
The 74F112 contains two independent, high-speed JK flip-
Asynchronous Inputs:
flops with Direct Set and Clear inputs. Synchronous state
LOW input to S sets Q to HIGH level
changes are initiated by the falling edge of the clock. Trig-
D
gering occurs at a voltage level of the clock and is not
LOW input to C sets Q to LOW level
D
directly related to the transition time. The J and K inputs
Clear and Set are independent of clock
can change when the clock is in either state without affect-
Simultaneous LOW on C and S makes both Q
ing the flip-flop, provided that they are in the desired state
D D
during the recommended setup and hold times relative to
and Q HIGH
the falling edge of the clock. A LOW signal on S or C
D D
prevents clocking and forces Q or Q HIGH, respectively.
Ordering Code:
Order Number Package Number Package Description
74F112SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F112PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Logic Symbols Connection Diagram
IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009472 www.fairchildsemi.comUnit Loading/Fan Out
U.L. Input I /I
IH IL
Pin Names Description
Output I /I
HIGH/LOW
OH OL
J , J , K , K Data Inputs 1.0/1.0 20 A/0.6 mA
1 2 1 2
CP , CP Clock Pulse Inputs (Active Falling Edge) 1.0/4.0 20 A/2.4 mA
1 2
C , C Direct Clear Inputs (Active LOW) 1.0/5.0 20 A/3.0 mA
D1 D2
S , S Direct Set Inputs (Active LOW) 1.0/5.0 20 A/3.0 mA
D1 D2
Q , Q , Q , Q Outputs 50/33.3 1 mA/20 mA
1 2 1 2
Truth Table
Inputs Outputs
S C
CP JK Q Q
D D
LH X X X H L
HL X X X L H
LL X X X H H
HH hh Q Q
0 0
HH lh L H
HH hl H L
HH ll Q Q
0 0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Clock Transition
Q (Q ) = Before HIGH-to-LOW Transition of Clock
0 0
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F112