ECLSOIC8EVB ON Semiconductor

ECLSOIC8EVB Evaluation Board User s Manual for High Frequency SOIC 8 ECLSOIC8EVB LAYUP DETAIL 4 LAYER SILKSCREEN (TOP SIDE) LAYER 1 (TOP SIDE) 0.062 0.007 ROGERS 4003 0.008 in LAYER 2 (GROUND AND VEE PLANE P1) 1 OZ FR4 0.020 in LAYER 3 (GROUND AND VCC PLANE P2) 1 OZ FR4 0.025 in LAYER 4 (BOTTOM SIDE) Figure 2. Evaluation Board Layup Board Layout devices and the relevant configuration that utilizes this PCB The 8lead SOIC evaluation board was designed to be board. List of components and simple schematics are located versatile and accommodate several different configurations. in Figures 4 through 14. Place SMA connectors on J1 The input, output, and power pin layout of the evaluation through J7, 50 chip resistors on R1 through R7, and chip board is shown in Figure 3. The evaluation board has at least capacitors C1 through C4 according to configuration eleven possible configurable options. Table 1. list the figures. (C1 and C2 are 0.01 F and C3 and C4 are 0.1 F). Top View Bottom View Figure 3. Evaluation Board Layout