ECLTSSOP20EVB ON Semiconductor

ECLTSSOP20EVB Evaluation Board User s Manual for High Frequency TSSOP 20 ECLTSSOP20EVB Bottom View Expanded Bottom View Figure 2. Bottom View of the 20lead TSSOP Evaluation Board LAYUP DETAIL 4 LAYER SILKSCREEN (TOP SIDE) LAYER 1 (TOP SIDE) 1 OZ ROGERS 4003 0.008 in LAYER 2 (GROUND PLANE P1) 1 OZ FR4 0.020 in 0.062 0.007 LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ FR4 0.025 in LAYER 4 (BOTTOM SIDE) 1 OZ Figure 3. Evaluation Board Layup Board Layout The 20lead TSSOP evaluation board was designed to be board. Lists of components and simple schematics are versatile and accommodate several different configurations. located in Figures 6 through 12. Place SMA connectors on The input, output, and power pin layout of the evaluation J1 through J20, 50 chip resistors between ground pad and board is shown in Figures 4 and 5. The evaluation board has Pin 1 pad through Pin 20 pad, and chip capacitors C1 through at least eight possible configurable options. Table 1, list the C5 according to configuration figures. (C4 and C5 are 0.01 devices and the relevant configuration that utilizes this PCB F and C1, C2, and C3 are 0.1 F) (See Figure 5).