NBSG53A 2.5V/3.3VSiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS* NBSG53A 12 3 4 V R SEL OLS CC Exposed Pad 16 15 14 13 (EP) VTD D D VTD A VTCLK V 1 12 EE B CLK VTCLK V Q CC 2 11 CLK Q NBSG53A CLK Q 3 10 C VTCLK CLK V Q EE VTCLK V 4 9 CC V R SEL OLS CC D 56 7 8 VTD D D VTD Figure 1. BGA16 Pinout (Top View) Figure 2. QFN16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin BGA QFN Name I/O Description C2 1 VTCLK Internal 50 Termination Pin. See Table 4. C1 2 CLK ECL, CML, Inverted Differential Input. LVCMOS, LVDS, LVTTL Input B1 3 CLK ECL, CML, Noninverted Differential Input. LVCMOS, LVDS, LVTTL Input B2 4 VTCLK Internal 50 Termination Pin. See Table 4. A1 5 VTD Internal 50 termination pin. See Table 4. A2 6 D ECL, CML, Inverted Differential Input. LVCMOS, LVDS, LVTTL Input A3 7 D ECL, CML, Noninverted Differential Input. LVCMOS, LVDS, LVTTL Input A4 8 VTD Internal 50 Termination Pin. See Table 4. D1,B3 9,16 V Positive Supply Voltage CC B4 10 Q RSECL Output NonInverted Differential Output. Typically Terminated with 50 Resistor to V = V 2 V. TT CC C4 11 Q RSECL Output Inverted Differential Output. Typically Terminated with 50 Resistor to V = V 2 V. TT CC C3 12 V Negative Supply Voltage EE D4 13 OLS* Input Input Pin for the Output Level Select (OLS). See Table 2. D3 14 SEL LVECL, LVCMOS, Select Logic Input. Internal 75 k to V . EE LVTTL Input D2 15 R LVECL, LVCMOS, Reset D FlipFlop. Internal 75 k to V . EE LVTTL Input N/A EP The Exposed Pad (EP) and the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heatsinking conduit. The pad is not electrically connected to the die but may be electrically and thermally connected to V on the PC board. EE 1. All V and V pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on CC EE package bottom (see case drawing) must be attached to a heatsinking conduit. 2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self oscillation. 3. When an output level of 400 mV is desired and V V > 3.0 V, 2K resistor should be connected from OLS pin to V . CC EE EE