DATA SHEET www.onsemi.com P-Channel Logic Level D Enhancement Mode Field G Effect Transistor S SOT23/SUPERSOT23, 3 LEAD, 1.4x2.9 CASE 527AG NDS352AP MARKING DIAGRAM General Description These P Channel logic level enhancement mode power field effect Drain transistors are produced using onsemis proprietary, high cell density, 3 DMOS technology. This very high density process is especially 352A(M) tailored to minimize on state resistance. These devices are particularly suited for low voltage applications such as notebook 12 computer power management, portable electronics, and other battery Gate Source powered circuits where fast highside switching, and low in line M = Date Code power loss are needed in a very small outline surface mount package. Features S 0.9 A, 30 V R = 0.5 V = 4.5 V DS(on) GS R = 0.3 V = 10 V DS(on) GS G Industry Standard Outline SOT23 Surface Mount Package Using Proprietary SUPERSOT 3 Design for Superior Thermal and Electrical Capabilities High Density Cell Design for Extremely Low R DS(on) D Exceptional OnResistance and Maximum DC Current Capability PChannel MOSFET This is a PbFree Device ORDERING INFORMATION Device Package Shipping NDS352AP SOT233/ 3000 / SUPERSOT23 Tape & Reel (PbFree) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 1997 1 Publication Order Number: December, 2021 Rev. 5 NDS352AP/DNDS352AP ABSOLUTE MAXIMUM RATINGS T = 25C unless otherwise noted. A Symbol Parameter Ratings Unit V DrainSource Voltage 30 V DSS V GateSource Voltage Continuous 20 V GSS I Maximum Drain Current Continuous (Note 1a) 0.9 A D Maximum Drain Current Pulsed 10 P Maximum Power Dissipation (Note 1a) 0.5 W D Maximum Power Dissipation (Note 1b) 0.46 T , T Operating and Storage Temperature Range 55 to +150 C J STG Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL CHARACTERISTICS Symbol Parameter Ratings Unit R Thermal Resistance, JunctiontoAmbient (Note 1a) 250 C/W JA Thermal Resistance, JunctiontoCase (Note 1) 75 C/W R JC 1. R is the sum of the junctiontocase and casetoambient thermal resistance where the case thermal reference is defined as the solder JA mounting surface of the drain pins. R is guaranteed by design while R is determined by the users board design. JC CA T T T T J A J A 2 P (t) I (t) R D D DS(ON) T J R (t) R R (t) JA JC CA Typical R using the board layouts shown below on 4.5x 5 FR4 PCB in a still air environment: JA 2 2 a) 250C/W when mounted on a 0.02 in pad b) 270C/W when mounted on a 0.001 in pad of 2oz copper. of 2oz copper. www.onsemi.com 2