NTMFD4C85N PowerPhase, Dual N-Channel SO8FL 30 V, High Side 25 A / Low Side 49 A Features CoPackaged Power Stage Solution to Minimize Board Space www.onsemi.com Minimized Parasitic Inductances Optimized Devices to Reduce Power Losses V R MAX I MAX (BR)DSS DS(ON) D These Devices are PbFree, Halogen Free/BFR Free and are RoHS 3.0 m 10 V Q1 Top FET Compliant 25 A 30 V 4.3 m 4.5 V Applications 0.8 m 10 V DCDC Converters Q2 Bottom FET 49 A 30 V 1.2 m 4.5 V System Voltage Rails Point of Load D1 (3, 4, 9) (1) G1 (2) S1 SW (5, 6, 7) (8) G2 S2 (10) Figure 1. Typical Application Circuit PIN CONNECTIONS D1 4 5 SW 100 9 10 D1 3 6 SW D1 S2 95 S1 2 7 SW G1 1 8 G2 90 (Bottom View) 85 MARKING DIAGRAM 80 V = 12 V IN 1 V = 1.2 V OUT DFN8 4C85N V = 5 V GS 75 CASE 506CR AYWZZ F = 300 kHz SW 1 T = 25C A 70 0 5 10 15 20 25 30 4C85N = Specific Device Code LOAD CURRENT (A) A = Assembly Location Figure 2. Typical Efficiency Performance Y = Year POWERPHASEGEVB Evaluation Board W = Work Week ZZ = Lot Traceability ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: February, 2016 Rev. 2 NTMFD4C85N/D EFFICIENCY (%)NTMFD4C85N Table 1. MAXIMUM RATINGS (TJ=25C unless otherwise stated) Parameter Symbol Value Units DraintoSource Voltage Q1 V 30 V DSS Q2 GatetoSource Voltage Q1 V 20 V GS Q2 Continuous Drain Current R (Note 1) T = 25C Q1 I 20.1 A JA A D T = 85C 14.5 A T = 25C Q2 39 A T = 85C 28.1 A Power Dissipation P 1.95 W Q1 D R (Note 1) T = 25C JA A Q2 Continuous Drain Current R 10 s (Note 1) T = 25C Q1 I 25.4 A JA A D T = 85C 18.3 A T = 25C Q2 49.2 A T = 85C 35.5 A Power Dissipation Q1 P 3.10 W D Steady T = 25C R 10 s (Note 1) JA A State Q2 Continuous Drain Current T = 25C Q1 I 15.4 A A D R (Note 2) JA T = 85C 11.1 A T = 25C Q2 29.7 A T = 85C 21.4 A Power Dissipation Q1 P 1.13 W D T = 25C R (Note 2) JA A Q2 Continuous Drain Current I A Q1 67 D R JC Q2 174 T = 25C C Power Dissipation Q1 P 22 W D R JC Q2 40 Pulsed Drain Current Q1 I 300 A DM T = 25C A tp = 10 s Q2 525 Operating Junction and Storage Temperature Q1 T , T 55 to +150 C J STG Q2 Source Current (Body Diode) Q1 I 10 A S Q2 10 Drain to Source DV/DT dV/dt 6 V/ns Single Pulse DraintoSource Avalanche Energy (T = 25C, mJ I = 19 A Q1 EAS 34.5 J L pk V = 50 V, V = 10 V, L = 0.1 mH, R = 25 ) DD GS G I = 26 A Q2 EAS 222 L pk Lead Temperature for Soldering Purposes (1/8 from case for 10 s) T 260 C L Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Surfacemounted on FR4 board using 1 sqin pad, 2 oz Cu. 2 2. Surfacemounted on FR4 board using the minimum recommended pad size of 100 mm . www.onsemi.com 2