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This literature is subject to all applicable copyright laws and is not for resale in any manner.SS U1N50B - N-Channel B-FET MOSFET April 2014 SSU1N50B 520V N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect 1.3A, 520V, R = 5.3 V = 10 V DS(on) GS transistors are produced using Fairchilds proprietary, Low Gate Charge (Typ. 8.3 nC) planar, DMOS technology. Low Crss (Typ. 5.5 pF) This advanced technology has been especially tailored to Fast Switching minimize on-state resistance, provide superior switching 100% Avalanche Tested performance, and withstand high energy pulse in the Improved dv/dt Capability avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supplies, power factor correction and electronic lamp ballasts based on half bridge. D G G D S I-PAK S Absolute Maximum Ratings T = 25C unless otherwise noted C Symbol Parameter SSU1N50BTU Unit V Drain-Source Voltage 520 V DSS I - Continuous (T = 25C) Drain Current 1.3 A D C - Continuous (T = 100C) 0.82 A C I (Note 1) Drain Current - Pulsed 5.0 A DM V Gate-Source Voltage 30 V GSS E (Note 2) Single Pulsed Avalanche Energy 100 mJ AS I Avalanche Current (Note 1) 1.3 A AR E (Note 1) Repetitive Avalanche Energy 2.6 mJ AR dv/dt Peak Diode Recovery dv/dt (Note 3) 5.5 V/ns Power Dissipation (T = 25C) * 2.5 W P A D Power Dissipation (T = 25C) 26 W C - Derate above 25C 0.21 W/C T , T Operating and Storage Temperature Range -55 to +150 C J stg Maximum lead temperature for soldering purposes, T 300 C L 1/8 from case for 5 seconds Thermal Characteristics Symbol Parameter SSU1N50BTU Unit R Thermal Resistance, Junction-to-Case, Max. 4.76 C/W JC 2 R Thermal Resistance, Junction-to-Ambient (*1 in Pad of 2-oz Copper), Max 50 C/W JA R Thermal Resistance, Junction-to-Ambient (Minimum Pad of 2-oz Copper), Max. 110 C/W JA 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com 1 SSU1N50B Rev. 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