TSM4424 20V N-Channel MOSFET SOP-8 Key Parameter Performance Pin Definition: 1. Source 8. Drain Parameter Value Unit 2. Source 7. Drain 3. Source 6. Drain V 20 V DS 4. Gate 5. Drain R (max) 30 m DS(on) Q 11.2 nC g Features Block Diagram Advance Trench Process Technology High Density Cell Design for Ultra Low On-resistance Application Specially Designed for Li-on Battery Packs Battery Switch Application Ordering Information Part No. Package Packing TSM4424CS RLG SOP-8 2.5Kpcs / 13 Reel TSM4424CS RVG SOP-8 3Kpcs / 13 Reel N-Channel MOSFET Note: G denotes for Halogen- and Antimony-free as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds Absolute Maximum Ratings (T = 25C, unless otherwise noted) C Parameter Symbol Limit Unit Drain-Source Voltage V 20 V DS Gate-Source Voltage V 8 V GS Continuous Drain Current I 8 A D (Note 1) Pulsed Drain Current I 30 A DM Continuous Source Current (Diode Conduction) I 2.2 A S Ta = 25C 2.5 Maximum Power Dissipation P W D Ta = 75C 1.3 Operating Junction Temperature T +150 C J Operating Junction and Storage Temperature Range T , T -55 to +150 C J STG Thermal Performance Parameter Symbol Limit Unit Thermal Resistance Junction to Foot R 25 C/W JF Thermal Resistance Junction to Ambient R 52.5 C/W JA Document Number: DS P0000093 1 Version: D15 TSM4424 20V N-Channel MOSFET Electrical Specifications Parameter Conditions Symbol Min Typ Max Unit (Note 2) Static Drain-Source Breakdown Voltage V = 0V, I = 250uA BV 20 -- -- V GS D DSS Gate Threshold Voltage V = V , I = 250uA V -- 0.65 1 V DS GS D GS(TH) Gate Body Leakage V = 8V, V = 0V I -- -- 100 nA GS DS GSS Zero Gate Voltage Drain Current V = 20V, V = 0V I -- -- 1.0 uA DS GS DSS On-State Drain Current V =5V, V = 4.5V I 30 -- -- A DS GS D(ON) V = 4.5V, I = 4.5A -- 23 30 GS D Drain-Source On-State Resistance V = 2.5V, I = 3.5A R -- 25 35 m GS D DS(ON) V = 1.8V, I = 2.0A -- 35 45 GS D Forward Transconductance V = 10V, I = 6A g -- 40 -- S DS D fs Diode Forward Voltage I = 1.7A, V = 0V V -- 0.8 1.2 V S GS SD (Note 3) Dynamic Total Gate Charge Q -- 11.2 14 g V = 10V, I = 4.5A, DS D nC Gate-Source Charge Q -- 1.4 -- gs V = 4.5V GS Gate-Drain Charge Q -- 2.2 -- gd Input Capacitance C -- 500 -- iss V = 10V, V = 0V, DS GS Output Capacitance C -- 300 -- pF oss f = 1.0MHz Reverse Transfer Capacitance C -- 140 -- rss (Note 4) Switching Turn-On Delay Time t -- 15 25 d(on) V = 10V, R = 10, DD L Turn-On Rise Time t -- 30 60 r I = 1A, V = 4.5V, ns D GEN Turn-Off Delay Time t -- 35 70 d(off) R = 6 G Turn-Off Fall Time t -- 15 45 f Notes: 1. Pulse width limited by the maximum junction temperature 2. Pulse test: PW 300s, duty cycle 2% 3. For DESIGN AID ONLY, not subject to production testing. 4. Switching time is essentially independent of operating temperature. Document Number: DS P0000093 2 Version: D15