TSM4953D 30V Dual P-Channel MOSFET SOP-8 Pin Definition: PRODUCT SUMMARY 1. Source 1 8. Drain 1 2. Gate 1 7. Drain 1 V (V) R (m) I (A) DS DS(on) D 3. Source 2 6. Drain 2 60 V = 10V -4.9 GS 4. Gate 2 5. Drain 2 -30 90 V = 4.5V -3.7 GS Features Block Diagram Advance Trench Process Technology High Density Cell Design for Ultra Low On-resistance Application Load Switch PA Switch Ordering Information Part No. Package Packing TSM4953DCS RLG SOP-8 2.5Kpcs / 13 Reel Dual P-Channel MOSFET Note: G denotes Halogen Free Product. Absolute Maximum Rating (Ta = 25C unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage V -30 V DS Gate-Source Voltage V 20 V GS Continuous Drain Current, V 4.5V. I -4.9 A GS D Pulsed Drain Current, V 4.5V I -20 A GS DM a,b Continuous Source Current (Diode Conduction) I -2.6 A S Ta = 25C 2.5 Maximum Power Dissipation P W D Ta = 70C 1.3 Operating Junction Temperature T +150 C J Operating Junction and Storage Temperature Range T , T - 55 to +150 C J STG Thermal Performance Parameter Symbol Limit Unit Junction to Case Thermal Resistance R 40 C/W JC Junction to Ambient Thermal Resistance (PCB mounted) R 62.5 C/W JA Notes: a. Pulse width limited by the Maximum junction temperature b. Surface Mounted on FR4 Board, t 5 sec. Document Number: DS P0000106 1 Version: D15 TSM4953D 30V Dual P-Channel MOSFET Electrical Specifications (Ta = 25C unless otherwise noted) Parameter Conditions Symbol Min Typ Max Unit Static Drain-Source Breakdown Voltage V = 0V, I = -250uA BV -30 -- -- GS D DSS V Gate Threshold Voltage V = V , I = -250A V -1.0 -1.5 -3.0 V DS GS D GS(TH) Gate Body Leakage V = 20V, V = 0V I -- -- 100 nA GS DS GSS Zero Gate Voltage Drain Current V = -24V, V = 0V I -- -- -1.0 DS GS DSS A a On-State Drain Current V =-5V, V = -10V I -6 -- -- DS GS D(ON) A V = -10V, I = -4.9A -- 50 60 GS D a Drain-Source On-State Resistance R m DS(ON) V = -4.5V, I = -3.7A -- 75 90 GS D a Forward Transconductance V = -15V, I = -4.9A g -- 10 -- S DS D fs Diode Forward Voltage I = -1.9A, V = 0V V -- -- -1.3 V S GS SD Dynamic Total Gate Charge Q -- 28 -- g V = -15V, I = -4.9A, DS D nC Gate-Source Charge Q -- 3 -- gs V = -10V GS Gate-Drain Charge Q -- 7 -- gd Input Capacitance C -- 745 -- iss V = -15V, V = 0V, DS GS pF Output Capacitance C -- 440 -- oss f = 1.0MHz Reverse Transfer Capacitance C -- 120 -- rss Switching Turn-On Delay Time t -- -- d(on) 9 V = -15V, R = 15, DD L Turn-On Rise Time t -- 15 -- r I = -1A, V = -10V, nS D GEN Turn-Off Delay Time t -- 75 -- d(off) R = 6 G Turn-Off Fall Time t -- 40 -- f Notes: 1. pulse test: PW 300S, duty cycle 2% 2. For DESIGN AID ONLY, not subject to production testing. 3. Switching time is essentially independent of operating temperature. Document Number: DS P0000106 2 Version: D15