TSM4NB60 Taiwan Semiconductor N-Channel Power MOSFET 600V, 4.0A, 2.5 FEATURES KEY PERFORMANCE PARAMETERS 100% Avalanche Tested PARAMETER VALUE UNIT Pb-free plating V 600 V DS Compliant to RoHS Directive 2011/65/EU and in R (max) 2.5 DS(on) accordance to WEE 2002/96/EC Q 14.5 nC g Halogen-free according to IEC 61249-2-21 definition APPLICATION Power Supply Lighting ITO-220 TO-251 (IPAK) TO-251S (IPAK SL) TO-252 (DPAK) Notes: MSL 3 (Moisture Sensitivity Level) for TO-252 (D-PAK) per J-STD-020 ABSOLUTE MAXIMUM RATINGS (T = 25C unless otherwise noted) A PARAMETER SYMBOL IPAK/DPAK ITO-220 UNIT Drain-Source Voltage V 600 V DS Gate-Source Voltage V 30 V GS T = 25C 4.0 C (Note 1) Continuous Drain Current I A D T = 100C 2.4 C (Note 2) Pulsed Drain Current I 16 A DM Total Power Dissipation T = 25C P 50 25 W C DTOT (Note 3) Single Pulsed Avalanche Energy E 70 mJ AS (Note 3) Single Pulsed Avalanche Current I 4 A AS (Note 2) Repetitive Avalanche Energy E 5 mJ AR (Note 4) Peak Diode Recovery dV/dt 4.5 V/ns Operating Junction and Storage Temperature Range T , T - 55 to +150 C J STG THERMAL PERFORMANCE PARAMETER SYMBOL IPAK/DPAK ITO-220 UNIT Junction to Case Thermal Resistance R 2.5 5 C/W JC Junction to Ambient Thermal Resistance R 83 62.5 C/W JA Notes: R is the sum of the junction-to-case and case-to-ambient thermal resistances. The case thermal reference is defined JA at the solder mounting surface of the drain pins. R is guaranteed by design while R is determined by the users board JC CA design. R shown below for single device operation on FR-4 PCB in still air. JA 1 Version: L1901 TSM4NB60 Taiwan Semiconductor ELECTRICAL SPECIFICATIONS (T = 25C unless otherwise noted) A PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNIT (Note 5) Static Drain-Source Breakdown Voltage V = 0V, I = 250A BV 600 -- -- GS D DSS V Gate Threshold Voltage V = V , I = 250A V 2.5 3.5 4.5 V DS GS D GS(TH) Gate Body Leakage V = 30V, V = 0V I -- -- 100 GS DS GSS nA Zero Gate Voltage Drain Current V = 600V, V = 0V I -- -- 1 A DS GS DSS V = 10V, I = 2.0A -- 2.2 2.5 Drain-Source On-State Resistance GS D R DS(on) V = 40V, I = 2A g -- 2.6 -- S Forward Transfer Conductance DS D fs (Note 6) Dynamic Total Gate Charge Q -- 14.5 -- g V = 480V, I = 4.0A, DS D Gate-Source Charge Q -- 3.4 -- gs nC V = 10V GS Gate-Drain Charge Q -- 7 -- gd Input Capacitance C -- 500 -- iss V = 25V, V = 0V, DS GS pF Output Capacitance C -- 53.2 -- oss f = 1.0MHz Reverse Transfer Capacitance C -- 7 -- rss (Note 7) Switching Turn-On Delay Time t -- 11 -- d(on) V = 300V, DD Turn-On Rise Time t -- 20 -- r R = 25, ns GEN Turn-Off Delay Time t -- 30 -- d(off) I = 4.0A, V = 10V, D GS Turn-Off Fall Time t -- 19 -- f (Note 5) Source-Drain Diode Forward On Voltage -- -- 1.13 V I = 4.0A, V = 0V V S GS SD Reverse Recovery Time -- 522 -- ns t rr V =0V, I = 2A GS S Reverse Recovery Charge -- 1.6 -- C dI /dt = 100A/s Q F rr Source Current I -- -- 4 A Integral reverse diode S Source Current (Pulse) in the MOSFET I -- -- 16 A SM Notes: 1. Current limited by package. 2. Pulse width limited by the maximum junction temperature. 3. L = 8mH, I = 4.0A, V = 50V, R = 25, Starting T = 25C. AS DD G J 100% Eas Test Condition: L = 8mH, I = 2A, V = 50V, R = 25, Starting T = 25C AS DD G J 4. I 4A, dI/dt 200A/s, V BV , Starting T = 25C. SD DD DSS J 5. Pulse test: PW 300s, duty cycle 2%. 6. For DESIGN AID ONLY, not subject to production testing. 7. Switching time is essentially independent of operating temperature. 2 Version: L1901