TSM60N750 600V, 6A, 0.75 N-Channel Power MOSFET TO-252 TO-251 Pin Definition: Key Parameter Performance 1. Gate (DPAK) (IPAK) 2. Drain Parameter Value Unit 3. Source V 600 V DS R (max) 0.75 DS(on) Q g 10.8 nC Block Diagram Features Super-Junction technology High performance due to small figure-of-merit High ruggedness performance High commutation performance Application Power Supply. Lighting Ordering Information Part No. Package Packing N-Channel MOSFET TSM60N750CH C5G TO-251 75pcs / Tube TSM60N750CP ROG TO-252 2.5kpcs / 13 Reel Note: G denotes for Halogen- and Antimony-free as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds o Absolute Maximum Ratings (T =25 C unless otherwise noted) A Limit Parameter Symbol Unit IPAK/DPAK Drain-Source Voltage V 600 V DS Gate-Source Voltage V 30 V GS (Note 1) o Continuous Drain Current T = 25 C I 6 A C D (Note 2) Pulsed Drain Current I 18 A DM o Total Power Dissipation T =25 C P 62.5 W C DTOT (Note 3) Single Pulsed Avalanche Energy E 90 mJ AS (Note 3) Single Pulsed Avalanche Current I 1.9 A AS o Operating Junction and Storage Temperature Range T , T - 55 to +150 C J STG 1/7 Version: A14 Not Recommended TSM60N750 600V, 6A, 0.75 N-Channel Power MOSFET Thermal Performance Limit Parameter Symbol Unit IPAK/DPAK o Junction to Case Thermal Resistance R 2 C/W JC o Junction to Ambient Thermal Resistance R 62 C/W JA o Electrical Specifications (T =25 C unless otherwise noted) J Parameter Conditions Symbol Min Typ Max Unit (Note 4) Static Drain-Source Breakdown Voltage V = 0V, I = 250A BV 600 -- -- V GS D DSS Gate Threshold Voltage V = V , I = 250A V 2 3 4 V DS GS D GS(TH) Gate Body Leakage V = 30V, V = 0V I -- -- 100 GS DS GSS nA Zero Gate Voltage Drain Current V = 600V, V = 0V I -- -- 1 DS GS DSS A V = 10V, I = 3A -- 0.53 0.75 Drain-Source On-State Resistance GS D R DS(ON) (Note 5) Dynamic Total Gate Charge Q -- 10.8 -- g V = 380V, I = 6A, DS D Gate-Source Charge Q -- 2.7 -- gs nC V = 10V GS Gate-Drain Charge Q -- 3.7 -- gd Input Capacitance C -- 554 -- iss V = 100V, V = 0V, DS GS pF Output Capacitance f = 1.0MHz C -- 46 -- oss Gate Resistance f=1MHz, open drain R -- 2.7 -- g (Note 6) Switching Turn-On Delay Time t -- 17.3 -- d(on) V = 380V, DD Turn-On Rise Time t -- 22 -- r R = 25, ns GEN Turn-Off Delay Time t -- 28 -- d(off) I = 6A, V = 10V, D GS Turn-Off Fall Time t -- 22 -- f (Note 4) Source-Drain Diode Forward On Voltage -- -- 1.4 V I =6A, V =0V V S GS SD Reverse Recovery Time -- 182 -- ns t rr V =200V, I =3A R S Reverse Recovery Charge -- 1.3 -- C dI /dt=100A/s Q F rr Notes: 1. Current limited by package 2. Pulse width limited by the maximum junction temperature o 3. L=50mH, I =1.9A, V =50V, R =25, Starting T =25 C AS DD G J 4. Pulse test: PW 300s, duty cycle 2% 5. For DESIGN AID ONLY, not subject to production testing. 6. Switching time is essentially independent of operating temperature. 2/7 Version: A14 Not Recommended