SSM3K15AMFV TOSHIBA Field Effect Transistor Silicon N Channel MOS Type (U-MOS III) SSM3K15AMFV Load Switching Applications Unit: mm 2.5 V drive Low ON-resistance: R = 3.6 (max) ( V = 4 V) DS(ON) GS R = 6.0 (max) ( V = 2.5 V) DS(ON) GS 1.20.05 0.80.05 Absolute Maximum Ratings (Ta = 25C) 1 Characteristics Symbol Rating Unit 3 Drain-Source voltage V 30 V DSS 2 Gate-Source voltage V 20 V GSS DC I 100 D Drain current mA Pulse I 400 DP Drain dissipation P (Note 1) 150 mW D 1.Gate Channel temperature T 150 C ch 2.Source VESM Storage temperature range T 55 to 150 C stg 3.Drain Note: Using continuously under heavy loads (e.g. the application of JEDEC high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the JEITA reliability significantly even if the operating conditions (i.e. TOSHIBA 2-1L1B operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Weight: 1.5 mg (typ.) Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (Handling Precautions/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). 2 Note 1: Mounted on FR4 board (25.4 mm 25.4 mm 1.6 mm, Cu Pad: 0.585mm ) 0.5mm 0.45mm 0.45mm 0.4mm Marking Equivalent Circuit (top view) 3 3 D I 1 2 1 2 Start of commercial production 2010-06 1 2014-03-01 1.20.05 0.80.05 0.50.05 0.4 0.4 0.220.05 0.130.05 0.320.05SSM3K15AMFV Electrical characteristics (Ta = 25C) Characteristics Symbol Test Condition Min Typ. Max Unit V I = 0.1 mA, V = 0 V 30 (BR) DSS D GS Drain-Source breakdown voltage V V I = 0.1 mA, V = -10 V (Note 3) 16 (BR) DSX D GS Drain cut-off current I V = 30 V, V = 0 V 1 A DSS DS GS Gate leakage current I V = 16 V, V = 0 V 1 A GSS GS DS Gate threshold voltage V V = 3 V, I = 0.1 mA 0.8 1.5 V th DS D Forward transfer admittance Y V = 3 V, I = 10 mA (Note 2) 35 mS fs DS D I = 10 mA, V = 4 V (Note 2) 2.3 3.6 D GS Drain-Source ON-resistance R DS (ON) I = 10 mA, V = 2.5 V (Note 2) 3.5 6.0 D GS Input capacitance C 13.5 iss V = 3 V, V = 0 V, f = 1 MHz pF Output capacitance C 8.0 oss DS GS Reverse transfer capacitance C 6.5 rss Turn-on time t 5.5 on V = 5 V, I = 10 mA DD D Switching time ns V = 0 to 5 V, R = 50 GS G Turn-off time t 35 off Drain-source forward voltage V I = -100 mA, V = 0 V (Note 2) -0.85 -1.2 V DSF D GS Note 2: Pulse test Note 3: If a reverse bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drain-source breakdown voltage is lowered in this mode. Switching Time Test Circuit (a) Test circuit (b) V IN 5 V 90% V = 5 V DD 5 V OUT R = 50 G 10% IN 0 V Duty 1% 0 V : t , t < 5 ns IN r f (c) V OUT V DD Common source 90% 10 s Ta = 25C 10% V DD V DS (ON) t t r f t t on off Precaution V can be expressed as voltage between gate and source when low operating current value is I = 0.1 mA for this th D product. For normal switching operation, V requires higher voltage than V and V requires lower voltage GS (on) th GS (off) than V . (Relationship can be established as follows: V < V < V ) th GS (off) th GS (on) Please take this into consideration for using the device. Do not use this device under avalanche mode. It may cause the device to break down. Handling Precaution When handling individual devices (which are not yet mounting on a circuit board), be sure that the environment is protected against electrostatic electricity. Operators should wear anti-static clothing, and containers and other objects that come into direct contact with devices should be made of anti-static materials. Thermal resistance R and power dissipation P vary depending on board material, board area, board thickness th (ch-a) D and pad area. When using this device, please take heat dissipation into consideration 2 2014-03-01 R G