SSM6N7002BFU TOSHIBA Field-Effect Transistor Silicon N Channel MOS Type (U-MOS) SSM6N7002BFU High-Speed Switching Applications Analog Switch Applications Unit: mm 2.10.1 Small package 1.250.1 Low ON-resistance : R = 3.3 (max) ( V = 4.5 V) DS(ON) GS : R = 2.6 (max) ( V = 5 V) DS(ON) GS 1 6 : R = 2.1 (max) ( V = 10 V) DS(ON) GS 2 5 Absolute Maximum Ratings (Ta = 25C) (Q1, Q2 Common) 3 4 Characteristics Symbol Rating Unit Drain-source voltage V 60 V DSS Gate-source voltage V 20 V GSS DC I 200 D Drain current mA Pulse I 800 DP US6 Drain power dissipation (Ta = 25C) P (Note 1) 300 mW D 1.SOURCE1 4.SOURCE2 Channel temperature T 150 C ch 2.GATE1 5.GATE2 Storage temperature range T 55 to 150 C 3.DRAIN2 6.DRAIN1 stg Note: Using continuously under heavy loads (e.g. the application of high JEDEC temperature/current/voltage and the significant change in JEITA SC-88 temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. TOSHIBA 2-2J1C operating temperature/current/voltage, etc.) are within the Weight: 6.8 mg (typ.) absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (Handling Precautions/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1:Total rating, mounted on FR4 board 2 (25.4 mm 25.4 mm 1.6 mm, Cu Pad: 0.32mm 6) 0.4 mm Marking Equivalent Circuit (top view) 65 4 6 5 4 Q1 NM Q2 12 3 1 2 3 Start of commercial production 2009-08 1 2014-03-01 0.8 mm 2.00.2 1.30.1 0.90.1 0.65 0.65 0 to 0.1 0.150.05 +0.1 0.2 -0.05SSM6N7002BFU Electrical Characteristics (Ta = 25C) (Q1, Q2 Common) Characteristics Symbol Test Condition Min Typ MaxUnit Gate leakage current I V = 20 V, V = 0 V 10 A GSS GS DS V I =10 mA, V = 0 V 60 (BR) DSS D GS Drain-source breakdown voltage V V I = 10 mA, V = -10 V 45 (BR) DSX D GS Drain cutoff current I V = 60 V, V = 0 V 1 A DSS DS GS Gate threshold voltage V V = 10 V, I = 0.25 mA 1.5 3.1 V th DS D Forward transfer admittance Y V = 10 V, I = 200 mA (Note 2) 225 mS fs DS D I = 500 mA, V = 10 V (Note 2) 1.62 2.1 D GS Drain-source ON-resistance R I = 100 mA, V = 5 V (Note 2) 1.90 2.6 DS (ON) D GS I = 100 mA, V = 4.5 V (Note 2) 2.10 3.3 D GS Input capacitance C 17.0 iss Reverse transfer capacitance C V = 25 V, V = 0 V, f = 1 MHz 1.9 pF rss DS GS Output capacitance C 3.6 oss Turn-on delay time td 3.3 6.6 (on) V = 30 V , I = 200 mA , DD D Switching time ns V = 0 to 10 V GS Turn-off delay time td 14.5 40 (off) Drain-source forward voltage V I = -200 mA, V = 0 V (Note 2) -0.84 -1.2 V DSF D GS Note2: Pulse test Switching Time Test Circuit 10 V (a) Test circuit (b) V 90 % IN OUT 10 V 10 % IN 0 V 0 R L V DD (c) V 10 % OUT 10 s V DD V = 30 V DD 90 % Duty 1% V DS (ON) t t r f V : t , t < 2 ns IN r f (Z = 50 ) out td (on) Common Source td (off) Ta = 25 C Precaution Let V be the voltage applied between gate and source that causes the drain current (I ) to be low (0.25 mA for the th D SSM6N7002BFU). Then, for normal switching operation, V must be higher than V and V must be lower GS(on) th, GS(off) than V This relationship can be expressed as: V < V < V th. GS(off) th GS(on). Take this into consideration when using the device Handling Precaution When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that come into direct contact with devices should be made of antistatic materials. 2 2014-03-01 50