IRFD113 www.vishay.com Vishay Siliconix Power MOSFET FEATURES D For automatic insertion HVMDIP Compact plastic package End stackable G Fast switching Low drive current S G Easily paralleled S D Excellent temperature stability N-Channel MOSFET Material categorization: for definitions of compliance please see www.vishay.com/doc 99912 PRODUCT SUMMARY DESCRIPTION V (V) 60 DS The HVMDIP technology is the key to Vishays advance d R ()V = 10 V 0.8 DS(on) GS line of power MOSFET transistors. The efficient geometry Q (Max.) (nC) 7 g and unique processing of the HVMDIP design achieve s Q (nC) 2 gs very low on-state resistance combined with high Q (nC) 7 gd transconductance and extreme device ruggedness. Configuration Single HVMDIPs feature all of the established advantages of MOSFETs such as voltage control, very fast switching, ease of paralleling, and temperature stability of the electrical parameters. The HVMDIP 4 pin, dual-in-line package brings the advantages of HVMDIPs to high volume applications wher e automatic PC board insertion is desireable, such as circuit boards for computers, printers, telecommunications equipment, and consumer products. Their compatibility with automatic insertion equipment, low-profile and end stackable features represent the stat-of-the-art in powe r device packaging. ORDERING INFORMATION Package HVMDIP Lead (Pb)-free IRFD113PbF ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) C PARAMETER SYMBOLLIMITUNIT a Drain-source Voltage V 60 DS V Gate-source voltage V 20 GS Continuous drain current V at 10 V T = 25 C I 0.8 GS C D A b Pulsed drain current I 6.4 DM Linear derating factor 0.008 W/C Inductive current, clamped 6.4 A L = 100 H I LM Maximum power dissipation T = 25 C P 1.0 W C D Operating junction and storage temperature range T , T - 55 to + 150 J stg C c Soldering recommendations (peak temperature) for 10 s 300 Notes a. T = 25 C to 150 C J b. Repetitive rating pulse width limited by maximum junction temperature c. 1.6 mm from case S21-0886-Rev. B, 30-Aug-2021 Document Number: 91487 1 For technical questions, contact: hvm vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000IRFD113 www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOLTYP. MAX. UNIT Maximum Junction-to-Ambient R - 120 C/W thJA SPECIFICATIONS (T = 25 C, unless otherwise noted) C PARAMETER SYMBOL TEST CONDITIONS MIN.TYP.MAX.UNIT Static Drain-Source Breakdown Voltage V V = 0 V, I = 250 A 60 - - DS GS D V Gate-Source Threshold Voltage V V = V , I = 250 A 2.0 - 4.0 GS(th) DS GS D Gate-Source Leakage I V = 20 V - - 500 nA GSS GS V = max. rating, V = 0 V - - 250 DS GS Zero Gate Voltage Drain Current I A DSS V = max. rating x 0.8, V = 0 V, T = 125 DS GS C - - 1000 C b On-State Drain Current I V = 10 V V > I x R max. 0.8 - - A D(on) GS DS D(on) DS(on) b Drain-Source On-State Resistance R V = 10 V I = 0.8 A - 0.6 0.8 DS(on) GS D b Forward Transconductance g V > I x R max., I = 0.8 A 0.8 1.2 - S fs DS D(on) DS(on) D Dynamic Input Capacitance C - 135 200 iss V = 0 V, GS Output Capacitance C -V = 25 V, 80100 pF oss DS f = 1.0 MHz Reverse Transfer Capacitance C -2025 rss Total Gate Charge Q -5 7 g I = 4 A, D Gate-Source Charge Q -2V = 10 V - nC gs GS V = 0.8 max. rating DS Gate-Drain Charge Q -7- gd Turn-On Delay Time t -10 20 d(on) Rise Time t -15 25 r V = 0.5 V , I = 0.8 A, DD DS D ns R = 50 Turn-Off Delay Time t -1g 525 d(off) Fall Time t -1020 f D Internal Drain Inductance L Between lead, -4.0 - D 6 mm (0.25 ) from nH package and center of G Internal Source Inductance L -6.0 - S die contact S Drain-Source Body Diode Characteristics MOSFET symbol D Continuous Source-Drain Diode Current I -- 0.8 S showing the A G integral reverse Pulsed Diode Forward Current I -- 6.4 SM p - n junction diode S a Body Diode Voltage V T = 25 C, I = 0.8 A, V = 0 V - - 2 V SD A S GS Body Diode Reverse Recovery Time t - 100 - ns rr T = 150 C, I = 1.0 A, dI/dt = 100 A/s J F Body Diode Reverse Recovery Charge Q -0.2 - C rr Forward Turn-On Time t Intrinsic turn-on time is negligible (turn-on is dominated by L and L ) on S D Notes a. Repetitive rating pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width 300 s duty cycle 2 % S21-0886-Rev. B, 30-Aug-2021 Document Number: 91487 2 For technical questions, contact: hvm vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000