1.6 mm Si8902EDB www.vishay.com Vishay Siliconix Bi-Directional N-Channel 20 V (D-S) MOSFET FEATURES PRODUCT SUMMARY TrenchFET power MOSFET V (V) R ()I (A) S1S2 S1S2(on) S1S2 Ultra-low R SS(on) 0.045 at V = 4.5 V 5.0 GS ESD protected: 4000 V 0.048 at V = 3.7 V 4.8 GS 20 0.057 at V = 2.5 V 4.4 MICRO FOOT chipscale packaging reduces GS footprint area profile (0.62 mm) and on-resistance 0.072 at V = 1.8 V 3.9 GS per footprint area Material categorization: for definitions of compliance MICRO FOOT 2.4 x 1.6 S please see www.vishay.com/doc 99912 1 2 G 1 3 S APPLICATIONS 2 4 Battery protection circuit - 1-2 cell Li+/LiP battery pack for portable devices 1 S 6 1 G S 5 2 1 1 S 2 Backside View Bump Side View Marking Code: xxxx = 8902E G Ordering Information: 1 4 k Si8902EDB-T2-E1 (Lead (Pb)-free and halogen-free) 4 k G 2 S 2 N-Channel ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL 5 s STEADY STATE UNIT Source1- Source2 Voltage V 20 S1S2 V Gate-Source Voltage V 12 GS T = 25 C 53.9 Continuous Source1- Source2 Current A I S1S2 a (T = 150 C) J T = 85 C 3.4 2.8 A A Pulsed Source1- Source2 Current I 40 SM T = 25 C 1.7 1 A a Maximum Power Dissipation P W D T = 85 C 0.8 0.5 A Operating Junction and Storage Temperature Range T , T -55 to +150 C J stg c Package Reflow Conditions IR/Convection 260 THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYPICALMAXIMUMUNIT t 5 s 60 75 a Maximum Junction-to-Ambient R thJA Steady State 95 120 C/W b Maximum Junction-to-Foot Steady State R 18 22 thJF Notes a. Surface mounted on 1 x 1 FR4 board. b. The foot is defined as the top surface of the package. c. Refer to IPC/JEDEC (J-STD-020), no manual or hand soldering. S15-1171-Rev. J, 25-May-15 Document Number: 71862 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 8902E xxx 2.4 mmSi8902EDB www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN.TYP.MAX.UNIT Static Gate Threshold Voltage V V = V , I = 980 A 0.45 - 1 V GS(th) SS GS D V = 0 V, V = 4.5 V - - 4 A SS GS Gate-Body Leakage I GSS V = 0 V, V = 12 V - - 10 mA SS GS V = 20 V, V = 0 V - - 1 SS GS Zero Gate Voltage Source Current I A S1S2 V = 20 V, V = 0 V, T = 85 C - - 5 SS GS J a On-State Source Current I V = 5 V, V = 4.5 V 5 - - A S(on) SS GS V = 4.5 V, I = 1 A - 0.038 0.045 GS SS V = 3.7 V, I = 1 A - 0.041 0.048 GS SS a Source1-Source2 On State Resistance R S1S2(on) V = 2.5 V, I = 1 A - 0.048 0.057 GS SS V = 1.8 V, I = 1 A - 0.060 0.072 GS SS a Forward Transconductance g V = 10 V, I = 1 A - 20 - S fs SS SS b Dynamic Turn-On Delay Time t -1 1.5 d(on) Rise Time t -3 4.5 V = 10 V, R = 10 r SS L s I 1 A, V = 4.5 V, R = 6 Turn-Off Delay Time t -1SS GEN g 726 d(off) Fall Time t -10 15 f Notes a. Pulse test pulse width 300 s, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) 20 10 000 I at 25 C (mA) GSS 1000 16 100 12 T = 150 C J 10 8 1 T = 25 C J 4 0.1 0 0.01 0 36 9 12 15 0 3 6 9 12 15 V - Gate-to-Source Voltage (V) V - Gate-to-Source Voltage (V) GS GS Gate-Current vs. Gate-Source Voltage Gate Current vs. Gate-Source Voltage S15-1171-Rev. J, 25-May-15 Document Number: 71862 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 I - Gate Current (mA) GSS I - Gate Current (A) GSS