3.3 mm SiZF300DT www.vishay.com Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFET with Schottky Diode FEATURES PowerPAIR 3 x 3F TrenchFET Gen IV power MOSFET SkyFET low side MOSFET with integrated Schottky D 1 100 % R and UIS tested g S 2 Internally connected half-bridge configuration in 3.3 mm-by-3.3 mm footprint 1 2 G 1 Material categorization: for definitions of compliance 3 S /D 1 2 4 1 S /D please see www.vishay.com/doc 99912 1 2 G 2 V /D APPLICATIONS N-Channel 1 IN 1 Top View Bottom View MOSFET CPU core power PRODUCT SUMMARY G /G HS 1 Computer / server peripherals CHANNEL-1 CHANNEL-2 G Return/S V /S -D 1 1 SW 1 2 POL V (V) 30 30 DS R max. ( ) at V = 10 V 0.00450 0.00184 Synchronous buck converter DS(on) GS R max. ( ) at V = 4.5 V 0.00700 0.00257 DS(on) GS Schottky Telecom DC/DC G /G LS 2 Diode Q typ. (nC) 6.9 19.4 g a I (A) 75 141 D N-Channel 2 MOSFET GND/S Configuration Dual 2 ORDERING INFORMATION Package PowerPAIR 3 x 3F Lead (Pb)-free and halogen-free SiZF300DT-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1CHANNEL-2UNIT Drain-source voltage V 30 30 DS V Gate-source voltage V +20, -16 +16, -12 GS T = 25 C 75 141 C T = 70 C 60 113 C Continuous drain current (T = 150 C) I J D b, c b, c T = 25 C 23 34 A b, c b, c T = 70 C 18 27 A A Pulsed drain current (t = 100 s) I 150 200 DM T = 25 C 44 105 C Continuous source-drain diode current I S b, c b, c T = 25 C 3.4 6.2 A Single pulse avalanche current I 14 16 AS L = 0.1 mH Single pulse avalanche energy E 9.8 12.8 mJ AS T = 25 C 48 74 C T = 70 C 31 47 C Maximum power dissipation P W D b, c b, c T = 25 C 3.8 4.3 A b, c b, c T = 70 C 2.4 2.8 A Operating junction and storage temperature range T , T -55 to +150 J stg C d, e Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 26 33 23 29 thJA C/W Maximum junction-to-case (source) Steady state R 2 2.6 1.3 1.7 thJC Notes a. T = 25 C C b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR 3 x 3F is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 66 C/W for channel-1 and 67 C/W for channel-2 S18-0479-Rev. A, 30-Apr-2018 Document Number: 76288 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 3.3 mmSiZF300DT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN.TYP.MAX.UNIT Static Ch-1 30 - - Drain-source breakdown voltage V V = 0 V, I = 250 A DS GS D Ch-2 30 - - V Ch-1 1.1 - 2.2 Gate-source threshold voltage V V = V , I = 250 A GS(th) DS GS D Ch-2 1.0 - 2.2 V = 0 V, V = +20 V, -16 V Ch-1 - - 100 DS GS Gate-source leakage I nA GSS V = 0 V, V = +16 V, -12 V Ch-2 - - 100 DS GS Ch-1 - - 1 V = 30 V, V = 0 V DS GS Ch-2 - 30 350 Zero Gate voltage drain current I A DSS Ch-1 - - 5 V = 30 V, V = 0 V, T = 55 C DS GS J Ch-2 - 150 3000 Ch-1 10 - - b On-state drain current I V 5 V, V = 10 V A D(on) DS GS Ch-2 10 - - V = 10 V, I = 10 A Ch-1 - 0.00330 0.00450 GS D V = 10 V, I = 10 A Ch-2 - 0.00160 0.00184 GS D b Drain-source on-state resistance R DS(on) V = 4.5 V, I = 7 A Ch-1 - 0.00490 0.00700 GS D V = 4.5 V, I = 7 A Ch-2 - 0.00210 0.00257 GS D V = 10 V, I = 20 A Ch-1 - 60 - DS D b Forward transconductance g S fs V = 10 V, I = 20 A Ch-2 90 - DS D a Dynamic Ch-1 - 1100 - Input capacitance C iss Ch-2 - 3150 - Channel-1 Ch-1 - 530 - V = 15 V, V = 0 V, f = 1 MHz DS GS Output capacitance C pF oss Ch-2 - 1550 - Ch-1 - 40 - Reverse transfer capacitance C rss Channel-2 Ch-2 - 170 - V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-1 - 0.036 0.072 C /C ratio rss iss Ch-2 0.054 0.108 Ch-1 - 14.4 22 V = 15 V, V = 10 V, I = 10 A DS GS D Ch-2 - 41 62 Total gate charge Q g Ch-1 6.9 10.5 Channel-1 Ch-2 - 19.4 29 V = 15 V, V = 4.5 V, I = 10 A DS GS D Ch-1 - 3.1 - Gate-source charge Q nC gs Ch-2 - 7.1 - Channel-2 Ch-1 - 1.5 - Gate-drain charge Q V = 15 V, V = 4.5 V, I = 10 A gd DS GS D Ch-2 - 3.8 - Ch-1 - 13 - Output charge Q V = 15 V, V = 0 V oss DS GS Ch-2 - 40 - Ch-1 0.14 0.7 1.4 Gate resistance R f = 1 MHz g Ch-2 0.12 0.62 1.2 Ch-1 - 17 35 Turn-on delay time t d(on) Channel-1 Ch-2 - 25 50 V = 15 V, R = 3 DD L Ch-1 - 40 80 I 5 A, V = 4.5 V, R = 1 D GEN g Rise time t r Ch-2 - 53 110 Ch-1 - 23 45 Turn-off delay time t d(off) Channel-2 Ch-2 - 30 60 V = 15 V, R = 3 DD L Ch-1 - 7 15 I 5 A, V = 4.5 V, R = 1 Fall time t D GEN g f Ch-2 - 12 25 ns Ch-1 - 11 20 Turn-on delay time t d(on) Channel-1 Ch-2 - 13 25 V = 15 V, R = 3 DD L Ch-1 - 5 10 I 5 A, V = 10 V, R = 1 D GEN g Rise time t r Ch-2 - 20 40 Ch-1 - 23 45 Turn-off delay time t d(off) Channel-2 Ch-2 - 32 65 V = 15 V, R = 3 DD L Ch-1 - 5 10 I 5 A, V = 10 V, R = 1 Fall time t D GEN g f Ch-2 - 6 15 S18-0479-Rev. A, 30-Apr-2018 Document Number: 76288 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000