ANV32A62ASE1 T Anvo-Systems

ANV32A62ASE Anvo-Systems Dresden 64Kb Serial IC nvSRAM FEATURES DESCRIPTION The Anvo-Systems Dresden ANV32A62ASE is a 64Kb Two-Wire Serial Interface serial SRAM with a non-volatile SONOS storage ele- BI-directional Data Transfer Protocol ment included with each memory cell, organized as 8k words of 8 bits each. The devices are accessed by a 1MHz Clock Rate two-wire bus. Up to 4 cascadable devices can share Low Power Consumption the common bus. The ANV32A62ASE is accessed via Write Protection Pin for Hardware Data Protection a two-wire interface consisting of Serial Data / Address Internal 8192 x 8b Organized (SDA) and Serial Clock (SCL). All STORE cycles are self-timed. Block rollover WRITE at Bus Speed The serial nvSRAM provides the access and cycle times, easy to use and unlimited READ and WRITE Self-Timed PowerStore Cycle (8ms) endurance of a SRAM. Hardware Write-Protect Data transfers automatically to the non-volatile storage Unlimited READ and WRITE Cycles cells when power loss is detected or in any brown out 100k PowerStore Cycles situation (PowerStore). As long as power will be sup- 20-Year Non-volatile Data Retention plied within operating conditions all data stay volatile in 3.0V to 3.6V Power Supply the SRAM cells. Extended Temperature Range WRITE Protection of data in upper quarter of address space of the memory occurs when the Write Protect pin 8-pin 150 mil SOIC Packages is connected to V . CC RoHS-Compliant PIN CONFIGURATION BLOCK DIAGRAM 8 VCC VCAP 1 V CAP 7 A1 2 Voltage WP V CC Control nvSRAM V SS 6 A2 3 SCL Array 5 VSS 4 SDA 256 x 256 A1 A2 WP Control Logic Top View SCL 8-pin SOP 150 mil Column I/O Serial to Parallel SDA Converter Column Decoder PIN DESCRIPTION Address Counter / Decoder Signal Name Signal Description Address Inputs A1 - A2 SCL Serial Clock Serial Data / Address SDA WP Write Protect VCC Supply Voltage VCAP PowerStore Supply Voltage VSS Ground This product conforms to Anvo-Systems Dresden specifications Document Control Nr. 048 Rev 1.0 1 May, 2019 SOP Row DecoderANV32A62ASE noise immunity. An external pull-up resistor is required Pin Description to support the high level on the bus. Device Select Addresses (A2, A1): The 2 pins A1 - Serial Clock (SCL): The SCL input clocks in the data A2 are device address inputs to select 1 of up to 4 into the nvSRAM with the positive edge and with the devices of the same type on the same SCL / SDA bus. negative edge the data clocked out of the device. To select one device the hard wired addresses on the 2 pins have to match with the related bits in the slave Write Protect (WP): The WP input pin controls the address. Write access to the upper 16Kb of the memory. When WP is connected to ground the whole nvSRAM can be Serial Data / Address (SDA): The SDA pin is a bidi- written. If the pin is floating it will be internally pulled rectional pin for the data transfer. As output it is open down to ground. When WP is connected to V the CC drain and as input it will as Schmitt trigger to increase upper 16Kb are read-only. Memory Architecture Data Transfer: The ANV32A62ASE is a 64Kb serial nvSRAM 8Kb x 8 All address and data transfers take place while SCL is organized. It is using a standard two-wire interface high. Data on SDA may change only during SCL low (IC) and is functional similar to serial EEPROMs or phase. The SDA pin should not change while SCL is FRAM . The addressing requires a 13 bit address out high. All data transfers occur with MSB first. of the 2-byte address of the two-wire protocol. Acknowledge: Two-wire Interface All addresses and data words are serially transmitted to and from the ANV32A62ASE in 8-bit words. During The ANV32A62ASE is designed to support a bi-direc- th the 9 clock cycle the ANV32A62ASE sends a zero to tional two-wire bus protocol. Figure 1 below shows a acknowledge receipt of the byte or expect a zero from typical system configuration. the master to send the next byte. If there is no Any device sending data onto the bus is the transmitter acknowledge signal the condition is no-acknowledge and the target device is the receiver. The master con- and the operation is aborted. trols the bus and is generating the clock for all devices on the bus. All controlled devices are slaves and the Slave Address: ANV32A62ASE is a slave. After start condition the first byte is the slave address. The slave address contains in the bits 7 to 4 the slave ID (1010), in the bits 3 to 1 the device select address V CC bits and in bit 0 the selection for read or write operation. See Figure 2. Microcontroller 1 0 1 0 A2 A1 1 R/W SCL SDA SCL SDA ANV36A62 ANV36A62 A1 A2 A1 A2 MSB LSB Fig. 2: Device Address Fig.1: System configuration example Addressing Overview: Stop Condition The ANV32A62ASE uses the 2 device addresses A2 to Master must have the control over the two-wire bus, no A1 to allow up to 4 devices on the same bus. After memory READ can be in progress, to assert a stop acknowledge the device address from the selected condition. A stop condition is valid when the master device the master can send the 2 byte memory add- drives SDA from low to high when SCL is stable high. ress to the bus for a write operation. Internally the 13 All operations should end with such a stop condition. bit address will be latched. With each access the lat- Any operation which is in progress will be aborted. ched address will be incremented by 1. The current address is the value in the latch which is either a new Start Condition: written address or the address following the last access A start condition is indicated when the master drives as long as power is supported or a new address is SDA from high to low while SCL is stable high. All written in the latch. commands should be preceded by a start condi- Reads always use the current address. To start a tion.With a start condition any operation in progress random read a dummy write has to occur before. can be aborted at any time. Document Control Nr. 048 Rev 1.0 Anvo-Systems Dresden May 2019 2