74F1071MSA ON Semiconductor

74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device January 2008 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Features General Description 18-bit array structure in 20-pin package The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to pro- FAST Bipolar voltage clamping action tect more sensitive devices from electrical overstress Dual center pin grounds for min inductance due to electrostatic discharge (ESD). The inputs of the Robust design for ESD protection device aggressively clamp voltage excursions nominally Low input capacitance at 0.5V below and 7V above ground. Optimum voltage clamping for 5V CMOS/TTL applications Ordering Information Package Order Number Number Package Description 74F1071SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74F1071MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74F1071MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Connection Diagram Note: Simplified Component Representation 1994 Fairchild Semiconductor Corporation www.fairchildsemi.com 74F1071 Rev. 1.4.074F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating T Storage Temperature 65C to +150C STG Ambient Temperature Under Bias 65C to +125C T A T Junction Temperature Under Bias 65C to +150C J (1) V Input Voltage 0.5V to +6V I (1) Input Current 200mA to +50mA I I (2) ESD Human Body Model (MIL-STD-883D method 3015.7) 10kV IEC 801-2 6kV Machine Model (EIAJIC-121-1981) 2kV DC Latchup Source Current (JEDEC Method 17) 500mA Package Power Dissipation @ +70C SOIC Package 800mW Notes: 1. Voltage ratings may be exceeded if current ratings and junction temperature and power consumption ratings are not exceeded. 2. ESD Rating for Direct contact discharge using ESD Simulation Tester. Higher rating may be realized in the actual application. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Rating T Free Air Ambient Temperature 0C to +70C A V Reverse Bias Voltage 0V to 5.25 V Z DC Thermal Resistance (in Free Air) JA SOIC Package 100C/W SSOP Package 110C/W 1994 Fairchild Semiconductor Corporation www.fairchildsemi.com 74F1071 Rev. 1.4.0 2