STL3N10F7 STMicroelectronics

STL3N10F7 N-channel 100 V, 0.062 typ., 4 A STripFET VII DeepGATE Power MOSFET in a PowerFLAT 2x2 package Datasheet - production data Features Order code V R max I DS DS(on) D 1 2 STL3N10F7 100 V 0.07 4 A 3 N-channel enhancement mode 6 1 5 2 Low gate charge 4 3 100% avalanche rated PowerFLAT 2x2 Applications Switching applications Description Figure 1. Internal schematic diagram th 2(D) 3(G) 1(D) This device utilizes the 7 generation of design rules of STs proprietary STripFET technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest R in all DS(on) packages. D S 5(D) 4(S) 6(D) Bottom view AM11269v1 Table 1. Device summary Order code Marking Packages Packaging STL3N10F7 ST3N PowerFLAT 2x2 Tape and reel April 2014 DocID025948 Rev 2 1/13 This is information on a product in full production. www.st.comContents STL3N10F7 Contents 1 Electrical ratings 3 2 Electrical characteristics . 4 2.1 Electrical characteristics (curves) 6 3 Test circuits 8 4 Package mechanical data . 9 5 Revision history . 12 2/13 DocID025948 Rev 2