Si7812DN Vishay Siliconix N-Channel 75-V (D-S) MOSFET FEATURES PRODUCT SUMMARY Halogen-free According to IEC 61249-2-21 V (V) R ()I (A) Q (Typ.) DS DS(on) D g Available e 0.037 at V = 10 V 16 GS TrenchFET Power MOSFET 75 8 nC e 0.046 at V = 4.5 V GS 16 Low Thermal Resistance PowerPAK Package with Small Size and Low 1.07 mm Profile PowerPAK 1212-8 APPLICATIONS Primary Side Switch S 3.30 mm 3.30 mm 1 D S 2 S 3 G 4 D 8 D 7 G D 6 D 5 Bottom View S Ordering Information: Si7812DN-T1-E3 (Lead (Pb)-free) Si7812DN-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS T = 25 C, unless otherwise noted A Parameter Symbol LimitUnit V Drain-Source Voltage 75 DS V Gate-Source Voltage V 20 GS e T = 25 C 16 C e T = 70 C 16 C Continuous Drain Current (T = 150 C) I J D a, b T = 25 C A 7.2 a, b T = 70 C A 5.7 A Pulsed Drain Current I 25 DM e T = 25 C C 16 Continuous Source-Drain Diode Current I S a, b T = 25 C 3.2 A I Avalanche Current 15 AS L = 0.1 mH E Single-Pulse Avalanche Energy 11 mJ AS T = 25 C 52 C T = 70 C 33 C P Maximum Power Dissipation W D a, b T = 25 C 3.8 A a, b T = 70 C A 2.4 Operating Junction and Storage Temperature Range T , T - 55 to 150 J stg C c, d 260 Soldering Recommendations (Peak Temperature) Notes: a. Surface Mounted on 1 x 1 FR4 board. b. t = 10 s. c. See Solder Profile (www.vishay.com/ppg 73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. d. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. e. Package limited. Document Number: 73332 www.vishay.com S-83050-Rev. D, 29-Dec-08 1Si7812DN Vishay Siliconix THERMAL RESISTANCE RATINGS Parameter Symbol TypicalMaximumUnit a, b R Maximum Junction-to-Ambient t 10 s 26 33 thJA C/W R Maximum Junction-to-Case (Drain) Steady State 1.9 2.4 thJC Notes: a. Surface Mounted on 1 x 1 FR4 board. b. Maximum under Steady State conditions is 81 C/W. SPECIFICATIONS T = 25 C, unless otherwise noted J Parameter Symbol Test Conditions Min.Typ.Max.Unit Static V V = 0 V, I = 250 A Drain-Source Breakdown Voltage 75 V DS GS D V Temperature Coefficient V /T 65 DS DS J I = 250 A mV/C D V Temperature Coefficient V /T - 6.4 GS(th) GS(th) J V = V , I = 250 A 1.0 2.0 3.0 DS GS D Gate-Source Threshold Voltage V V GS(th) V = V , I = 5 mA 2.3 DS GS D I V = 0 V, V = 20 V Gate-Source Leakage 100 nA GSS DS GS V = 75 V, V = 0 V 1 DS GS I Zero Gate Voltage Drain Current A DSS V = 75 V, V = 0 V, T = 55 C 10 DS GS J a I V 5 V, V = 10 V On-State Drain Current 25 A D(on) DS GS V = 10 V, I = 7.2 A 0.031 0.037 GS D a R Drain-Source On-State Resistance DS(on) V = 4.5 V, I = 6.4 A 0.038 0.046 GS D a g V = 15 V, I = 7.2 A 23 S Forward Transconductance fs DS D b Dynamic C Input Capacitance 840 iss Output Capacitance C V = 35 V, V = 0 V, f = 1 MHz 110 pF oss DS GS C Reverse Transfer Capacitance 50 rss V = 38 V, V = 10 V, I = 7.2 A 16 24 DS GS D Total Gate Charge Q g 812 nC Q Gate-Source Charge V = 38 V, V = 4.5 V, I = 7.2 A 2.8 gs DS GS D Gate-Drain Charge Q 3.6 gd R Gate Resistance f = 1 MHz 1 g t Turn-On Delay Time 20 30 d(on) t Rise Time V = 38 V, R = 6.7 130 200 r DD L I 5.7 A, V = 4.5 V, R = 1 t Turn-Off Delay Time D GEN g 20 30 d(off) t Fall Time 50 75 f ns t Turn-On Delay Time 15 25 d(on) t Rise Time V = 38 V, R = 6.7 20 30 r DD L I 5.7 A, V = 10 V, R = 1 t Turn-Off Delay Time D GEN g 35 40 d(off) Fall Time t 10 15 f www.vishay.com Document Number: 73332 2 S-83050-Rev. D, 29-Dec-08