6.15 mm SiR882ADP www.vishay.com Vishay Siliconix N-Channel 100 V (D-S) MOSFET FEATURES PowerPAK SO-8 Single D TrenchFET power MOSFET D 8 D 7 100 % R and UIS tested g D 6 5 Material categorization: for definitions of compliance please see www.vishay.com/doc 99912 1 2 S 3 S APPLICATIONS D 4 S 1 G DC/DC primary side switch Top View Bottom View Telecom/server 48 V, full/half-bridge PRODUCT SUMMARY DC/DC V (V) 100 DS G Industrial R max. ( ) at V = 10 V 0.0087 DS(on) GS R max. ( ) at V = 7.5 V 0.0094 DS(on) GS R max. ( ) at V = 4.5 V 0.0115 DS(on) GS S Q typ. (nC) 19.5 g N-Channel MOSFET I (A) 60 D Configuration Single ORDERING INFORMATION Package PowerPAK SO-8 Lead (Pb)-free and halogen-free SiR882ADP-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL LIMITUNIT Drain-source voltage V 100 DS V Gate-source voltage V 20 GS a T = 25 C 60 C T = 70 C 55 C Continuous drain current (T = 150 C) I J D b, c T = 25 C 17.6 A b, c T = 70 C 13.9 A A Pulsed drain current (t = 300 s) I 80 DM a T = 25 C 60 C Continuous source-drain diode current I S b, c T = 25 C 4.9 A Single pulse avalanche current I 30 AS L = 0.1 mH Single pulse avalanche energy E 45 mJ AS T = 25 C 83 C T = 70 C 53 C Maximum power dissipation P W D b, c T = 25 C 5.4 A b, c T = 70 C 3.4 A Operating junction and storage temperature range T , T -55 to +150 J stg C d, e Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYPICALMAXIMUMUNIT b, f Maximum junction-to-ambient t 10 s R 18 23 thJA C/W Maximum junction-to-case (drain) Steady state R 11.5 thJC Notes a. Package limited b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 65 C/W S17-0407-Rev. B, 20-Mar-17 Document Number: 63367 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 5.15 mm SiR882ADP www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP.MAX.UNIT Static Drain-source breakdown voltage V V = 0 V, I = 250 A 100 - - DS GS D V c Drain-source breakdown voltage (transient) V V = 0 V, I = 30 A, t = 3 s 110 - - DS(transient) GS D(aval) transient V temperature coefficient V /T -67 - DS DS J I = 250 A mV/C D V temperature coefficient V /T --5.8 - GS(th) GS(th) J Gate-source threshold voltage V V = V , I = 250 A 1.2 - 2.8 V GS(th) DS GS D Gate-source leakage I V = 0 V, V = 20 V - - 100 nA GSS DS GS V = 100 V, V = 0 V - - 1 DS GS Zero gate voltage drain current I A DSS V = 100 V, V = 0 V, T = 55 C - - 10 DS GS J a On-state drain current I V 5 V, V = 10 V 30 - - A D(on) DS GS V = 10 V, I = 20 A - 0.0072 0.0087 GS D a Drain-source on-state resistance R V = 7.5 V, I = 17 A - 0.0077 0.0094 DS(on) GS D V = 4.5 V, I = 15 A - 0.0092 0.0115 GS D a Forward transconductance g V = 10 V, I = 20 A - 60 - S fs DS D b Dynamic Input capacitance C - 1975 - iss Output capacitance C V = 50 V, V = 0 V, f = 1 MHz - 748 - pF oss DS GS Reverse transfer capacitance C -60- rss V = 50 V, V = 10 V, I = 20 A - 39.5 60 DS GS D Total gate charge Q V = 50 V, V = 7.5 V, I = 20 A - 30.3 45.5 g DS GS D - 19.5 29.5 nC Gate-source charge Q V = 50 V, V = 4.5 V, I = 20 A -5.7 - gs DS GS D Gate-drain charge Q -8.3- gd Output charge Q V = 50 V, V = 0 V - 61 92 oss DS GS Gate resistance R f = 1 MHz 0.2 0.95 1.9 g Turn-on delay time t -11 22 d(on) Rise time t -12 24 r V = 50 V, R = 5 DD L I 10 A, V = 10 V, R = 1 Turn-off delay time t -3D GEN g 465 d(off) Fall time t -9 18 f ns Turn-on delay time t -13 26 d(on) Rise time t -14 24 r V = 50 V, R = 5 DD L I 10 A, V = 7.5 V, R = 1 Turn-off delay time t -3D GEN g 260 d(off) Fall time t -10 20 f Drain-Source Body Diode Characteristics Continuous source-drain diode current I T = 25 C - - 60 S C A a Pulse diode forward current I -- 80 SM Body diode voltage V I = 5 A - 0.74 1.1 V SD S Body diode reverse recovery time t -49 95 ns rr Body diode reverse recovery charge Q - 54 105 nC rr I = 10 A, dI/dt = 100 A/s, T = 25 C F J Reverse recovery fall time t -24 - a ns -25 - Reverse recovery rise time t b Notes a. Pulse test pulse width 300 s, duty cycle 2 % b. Guaranteed by design, not subject to production testing c. T = 25 C. Expected voltage stress during 100 % UIS test. Production datalog is not available CASE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S17-0407-Rev. B, 20-Mar-17 Document Number: 63367 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000