6 mm6 mm SiZ980DT www.vishay.com Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFET with Schottky Diode FEATURES PRODUCT SUMMARY TrenchFET Gen IV power MOSFET V (V) R ( ) (MAX.) I (A) Q (TYP.) DS DS(on) D g SkyFET low-side MOSFET with integrated a 0.0067 at V = 10 V 20 GS Schottky Channel-1 30 5.4 nC a 0.0100 at V = 4.5 V 20 GS 100 % R and UIS tested g a 0.0016 at V = 10 V 60 GS Channel-2 30 21 nC Material categorization: for definitions of a 0.0022 at V = 4.5 V 60 GS compliance please see www.vishay.com/doc 99912 PowerPAIR 6 x 5 G 2 APPLICATIONS D 1 S 2 8 S 2 7 CPU core power S 2 6 5 Computer / server peripherals S /D 1 2 G 1 (Pin 9) POL N-Channel 1 D 1 MOSFET S /D 1 2 1 Synchronous buck converter 2 G 1 3 D 1 Telecom DC/DC 4 11 D 1 Schottky D 1 Diode G 2 Top View Bottom View Ordering Information: N-Channel 2 MOSFET SiZ980DT-T1-GE3 (lead (Pb)-free and halogen-free) S 2 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1CHANNEL-2UNIT Drain-Source Voltage V 30 DS V Gate-Source Voltage V +20, -16 GS a a T = 25 C 20 60 C a a T = 70 C 20 60 C Continuous Drain Current (T = 150 C) I J D b, c b, c T = 25 C 18.8 43 A b, c b, c T = 70 C 14.6 34 A A Pulsed Drain Current (t = 100 s) I 90 130 DM a a T = 25 C 20 55 C Continuous Source-Drain Diode Current I S b, c b, c T = 25 C 3.2 4.1 A Single Pulse Avalanche Current I 15 25 AS L = 0.1 mH Single Pulse Avalanche Energy E 11.2 31 mJ AS T = 25 C 20 66 C T = 70 C 12.9 42 C Maximum Power Dissipation P W D b, c b, c T = 25 C 3.8 5 A b, c b, c T = 70 C 2.4 3.2 A Operating Junction and Storage Temperature Range T , T -55 to +150 J stg C d, e Soldering Recommendations (Peak Temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum Junction-to-Ambient t 10 s R 26 33 20 25 thJA C/W Maximum Junction-to-Case (Drain) Steady State R 4.7 6.2 1.5 1.9 thJC Notes a. Package limited. b. Surface mounted on 1 x 1 FR4 board. c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 68 C/W for channel-1 and 57 C/W for channel-2. S16-2419-Rev. C, 28-Nov-16 Document Number: 62976 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 5 mmSiZ980DT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN.TYP.MAX.UNIT Static Ch-1 30 - - Drain-Source Breakdown Voltage V V = 0 V, I = 250 A DS GS D Ch-2 30 - - c Ch-1 36 - - Drain-Source Breakdown Voltage V V = 0 V, t 1 s V GS transient DSt (transient) Ch-2 36 - - Ch-1 1.2 - 2.2 Gate-Source Threshold Voltage V V = V , I = 250 A GS(th) DS GS D Ch-2 1.1 - 2.2 Ch-1 - - 100 Gate-Source Leakage I V = 0 V, V = +20 V, -16 V nA GSS DS GS Ch-2 - - 100 Ch-1 - - 1 V = 30 V, V = 0 V DS GS Ch-2 - 20 100 Zero Gate Voltage Drain Current I A DSS Ch-1 - - 5 V = 30 V, V = 0 V, T = 55 C DS GS J Ch-2 - 100 1000 Ch-1 20 - - b On-State Drain Current I V 5 V, V = 10 V A D(on) DS GS Ch-2 20 - - V = 10 V, I = 15 A Ch-1 - 0.0047 0.0067 GS D V = 10 V, I = 19 A Ch-2 - 0.0011 0.0016 GS D b Drain-Source On-State Resistance R DS(on) V = 4.5 V, I = 12 A Ch-1 - 0.0065 0.0100 GS D V = 4.5 V, I = 15 A Ch-2 - 0.0016 0.0022 GS D V = 10 V, I = 15 A Ch-1 - 80 - DS D b Forward Transconductance g S fs V = 10 V, I = 19 A Ch-2 155 - DS D a Dynamic Ch-1 - 930 - Input Capacitance C iss Ch-2 - 4600 - Channel-1 Ch-1 - 325 - Output Capacitance C V = 15 V, V = 0 V, f = 1 MHz pF oss DS GS Ch-2 - 1700 - Ch-1 - 21 - Channel-2 Reverse Transfer Capacitance C rss Ch-2 - 115 - V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-1 - 0.023 0.046 C /C Ratio rss iss Ch-2 0.025 0.050 Ch-1 - 12 18 V = 15 V, V = 10 V, I = 19 A DS GS D Ch-2 - 51 77 Total Gate Charge Q g Ch-1 5.4 8.1 Channel-1 Ch-2 - 23 35 V = 15 V, V = 4.5 V, I = 19 A DS GS D Ch-1 - 3 - Gate-Source Charge Q nC gs Ch-2 - 12.2 - Channel-2 Ch-1 - 0.75 - V = 15 V, V = 4.5 V, I = 19 A DS GS D Gate-Drain Charge Q gd Ch-2 - 2.2 - Ch-1 - 10 - Output Charge Q V = 15 V, V = 0 V oss DS GS Ch-2 - 54 - Ch-1 0.3 1.5 3 Gate Resistance R f = 1 MHz g Ch-2 0.2 1 2 S16-2419-Rev. C, 28-Nov-16 Document Number: 62976 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000