SIZ988DT-T1-GE3 Vishay

6 mm6 mm SiZ988DT www.vishay.com Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFETs FEATURES PRODUCT SUMMARY TrenchFET Gen IV power MOSFETs V (V) R ( ) (MAX.) I (A) Q (TYP.) DS DS(on) D g 100 % R and UIS tested g g 0.0075 at V = 10 V 40 GS Channel-1 30 6.9 nC g Optimized Q /Q ratio improves switching gs gs 0.0120 at V = 4.5 V 32 GS characteristics 0.0041 at V = 10 V 60 GS Channel-2 30 15.4 nC Material categorization: 0.0052 at V = 4.5 V 60 GS for definitions of compliance please see PowerPAIR 6 x 5 G www.vishay.com/doc 99912 2 S 2 8 S 2 7 S APPLICATIONS D1 2 6 5 S /D 1 2 CPU core power (Pin 9) Computer / server peripherals G 1 D 1 1 POL N-Channel 1 2 G S /D 1 1 2 MOSFET 3 D 1 Synchronous buck converter 4 11 D 1 D 1 Telecom DC/DC Top View Bottom View G 2 Ordering Information: N-Channel 2 MOSFET SiZ988DT-T1-GE3 (lead (Pb)-free and halogen-free) S 2 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1CHANNEL-2UNIT Drain-Source Voltage V 30 DS V Gate-Source Voltage V +20, -16 GS g a T = 25 C 40 60 C g a T = 70 C 32 60 C Continuous Drain Current (T = 150 C) I J D b, c b, c T = 25 C 17.5 27 A b, c b, c T = 70 C 14 21.7 A A Pulsed Drain Current (t = 100 s) I 70 140 DM T = 25 C 16.8 33.6 C Continuous Source Drain Diode Current I S b, c b, c T = 25 C 3.2 4 A Single Pulse Avalanche Current I 10 20 AS L = 0.1 mH Single Pulse Avalanche Energy E 520 mJ AS T = 25 C 20.2 40 C T = 70 C 12.9 25.8 C Maximum Power Dissipation P W D b, c b, c T = 25 C 3.8 4.8 A b, c b, c T = 70 C 2.4 3.1 A Operating Junction and Storage Temperature Range T , T -55 to +150 J stg C d, e Soldering Recommendations (Peak Temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum Junction-to-Ambient t 10 s R 26 33 21 26 thJA C/W Maximum Junction-to-Case (Drain) Steady State R 4.7 6.2 2.5 3.1 thJC Notes a. Package limited b. Surface mounted on 1 x 1 FR4 board. c. t = 10 s. d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 68 C/W for channel-1 and 57 C/W for channel-2. g. T = 25 C. C S15-2567-Rev. A, 02-Nov-15 Document Number: 66937 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 5 mmSiZ988DT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP.MAX.UNIT Static V = 0 V, I = 250 A Ch-1 30 - - GS D Drain-Source Breakdown Voltage V V DS V = 0 V, I = 250 A Ch-2 30 - - GS D V = V , I = 250 A Ch-1 1.2 - 2.4 DS GS D Gate Threshold Voltage V V GS(th) V = V , I = 250 A Ch-2 1.1 - 2.2 DS GS D Ch-1 - - 100 Gate Source Leakage I V = 0 V, V = 20 V, -16 V nA GSS DS GS Ch-2 - - 100 Ch-1 - - 1 V = 30 V, V = 0 V DS GS Ch-2 - - 1 Zero Gate Voltage Drain Current I A DSS Ch-1 - - 10 V = 30 V, V = 0 V, T = 55 C DS GS J Ch-2 - - 10 Ch-1 25 - - b On-State Drain Current I V 5 V, V = 10 V A D(on) DS GS Ch-2 25 - - V = 10 V, I = 10 A Ch-1 - 0.0057 0.0075 GS D V = 10 V, I = 19 A Ch-2 - 0.0028 0.0041 GS D b Drain-Source On-State Resistance R DS(on) V = 4.5 V, I = 8 A Ch-1 - 0.0077 0.0120 GS D V = 4.5 V, I = 15 A Ch-2 - 0.0040 0.0052 GS D V = 10 V, I = 10 A Ch-1 - 54 - DS D b Forward Transconductance g S fs V = 10 V, I = 10 A Ch-2 - 52 - DS D a Dynamic Ch-1 - 1000 - Input Capacitance C iss Ch-2 - 2425 - Ch-1 - 280 - Channel-1 Output Capacitance C pF oss V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-2 - 730 - Ch-1 - 34 - Channel-2 Reverse Transfer Capacitance C rss V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-2 - 65 - Ch-1 - 0.034 0.068 C / C Ratio rss iss Ch-2 - 0.027 0.054 Ch-1 - 14.3 21.5 V = 15 V, V = 10 V, I = 10 A DS GS D Ch-2 - 34 51 Total Gate Charge Q g Ch-1 - 6.9 10.5 Ch-2 - 15.4 23.1 Channel-1 V = 15 V, V = 4.5 V, I = 10 A DS GS D Ch-1 - 2.8 - Gate-Source Charge Q nC gs Ch-2 - 5.8 - Channel-2 V = 15 V, V = 4.5 V, I = 10 A DS GS D Ch-1 - 1.6 - Gate-Drain Charge Q gd Ch-2 - 2.6 - Ch-1 - 7.8 - Output Charge Q V = 15 V, V = 0 V oss DS GS Ch-2 - 20 - Ch-1 0.4 1.6 3.2 Gate Resistance R f = 1 MHz g Ch-2 0.3 1.7 3.4 S15-2567-Rev. A, 02-Nov-15 Document Number: 66937 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000