ANV32C81A Anvo-Systems Dresden 256kb Serial SPI nvSRAM FEATURES DESCRIPTION The Anvo-Systems Dresden ANV32C81A is a 256kb compatible with Serial Peripheral Interface (SPI) serial SRAM with a non-volatile SONOS storage ele- ment included with each memory cell, organized as Supports SPI Modes 0 and 3 32k words of 8 bits each. The devices are accessed by a high speed SPI-compatible bus. The ANV32C81A is 66MHz clock rate enabled through the Chip Enable pin (E) and accessed Block Write Protection via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO) and Serial Clock (SCK). Write Disable Instruction for Software Data Pro- All programming cycles are self-timed, and no separate ERASE cycle is required before STORE. tection The serial SRAM provides the fast access & cycle Secure WRITE times, ease of use and unlimited read & write endur- ance of a normal SRAM. Dedicated safety features Secure READ supporting high data accuracy. 2Byte User Serial Number With Secure WRITE operation the ANV32C81A accepts address and data only when the correct 2 Byte Hibernate Mode for low Standby Current CRC, generated from the 15 bit address and 64 Byte Page and block rollover options data, is transmitted. Corrupt data cannot overwrite existing memory content and even valid data would not Unlimited Read/Write Endurance overwrite on a corrupted address. With status register bit 4 the success of the Secure WRITE operation can Automatic Non-volatile STORE on Power Down be monitored. In case of corrupt data bit 4 will be set volatile to high. With Secure READ operation the Non-Volatile STORE under Instruction Control ANV32C81A calculates the correct 2 Byte CRC parallel Automatic RECALL to SRAM on Power Up to data transfer. The 2 Byte CRC is transmitted after 64 Bytes of data have been transmitted. Unlimited RECALL Cycles Data transfers automatically to the non-volatile storage cells when power loss is detected or in any brown out 100k STORE Cycles situation (the PowerStore operation). On power up, 100-Year Non-volatile Data Retention data is automatically restored to the SRAM (the Power Up Recall operation). 3.0V to 3.6V Power Supply The PowerStore operation can be deselected via Sta- Commercial and Industrial Temperatures tus Register settings. Both STORE and RECALL operations are also avail- 8-pin 150 mil SOIC and DFN Packages able under instruction control. RoHS-Compliant BLOCK WRITE Protection is enabled by programming the status register with one of four options to protect blocks. A 2 Byte non-volatile register supports the option of a 2 Byte user defined serial number. This register is under customer control only. Status register bit 5 will control page and block roll over modes. This product conforms to Anvo-Systems Dresden specifi- Document Control Nr. 039 Rev 1.0 cations 1 September, 2018ANV32C81A BLOCK DIAGRAM FLASH Array 512 x 512 V CC Power VCAP Store Control V SS SRAM Recall Array Store / 512 x 512 Recall Control Column I/O Data IO Register E Column Decoder HOLD SO Instruction Decode Control Logic SI SCK Address Counter / Decoder WP PIN CONFIGURATION PIN DESCRIPTIONS Signal Name Signal Description E 8 VCC 1 7 SO 2 HOLD Chip Enable E 6 SCK VCAP 3 SCK Serial Clock 5 VSS 4 SI Serial Input SI Top View Serial Output SO Hold (Suspends Serial HOLD 8-pin SOP 150 mil Input) VCC Power Supply Voltage VCAP Capacitor Voltage VSS Ground Serial Interface Description Master: The device that generates the serial clock. communication between a master and the device. Slave: Because the Serial Clock pin (SCK) is always Instructions, addresses, or data, present on the SI pin, an input, the device always operates as a slave. are latched on the rising edge of the clock input, while data on the SO pin is changed after the falling edge of Transmitter/Receiver: The device has separate pins the clock input. designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. Serial Output: The SO pin is used to transfer data serially out of the device. During a read cycle data is Serial Op-Code: After the device is selected with E shifted out on this pin after the falling edge of the Serial going low, the first byte will be received. This byte Clock. contains the op-code that defines the operations to be performed. Serial Input: The SI pin is used to transfer data serially into the device. It receives instructions, addresses, and Invalid Op-Code: If an invalid op-code is received, no data. Data is latched on the rising edge of the Serial data will be shifted into the device, and the serial output Clock. pin (SO) will remain in a high impedance state until the falling edge of E is detected. This will re-initialize the Serial Clock: The SCK pin is used to synchronize the serial communication. Document Control Nr. 039 Rev 1.0 Anvo-Systems Dresden September, 2018 2 SOP8 Row Decoder