ANV32C91A Anvo-Systems Dresden 512kb Serial SPI nvSRAM enabled through the Chip Enable pin (E) and accessed FEATURES via a 3-wire interface consisting of Serial Data Input compatible with Serial Peripheral Interface (SPI) (SI), Serial Data Output (SO) and Serial Clock (SCK). Supports SPI Modes 0 and 3 All programming cycles are self-timed, and no separate 66MHz clock rate ERASE cycle is required before STORE. Block Write Protection The serial SRAM provides the fast access & cycle times, ease of use and unlimited read & write endur- Write Disable Instruction for Software Data Pro- ance of a normal SRAM. Dedicated safety features tection supporting high data accuracy. Secure WRITE With Secure WRITE operation the ANV32C91A Secure READ accepts address and data only when the correct 2 Byte Hibernate Mode for low Standby Current CRC, generated from the 16 bit address and 64 Byte data, is transmitted. Corrupt data can not overwrite Unlimited Read/Write Endurance existing memory content and even valid data would not Automatic Non-volatile STORE on Power Down overwrite on a corrupted address. With status register Non-Volatile STORE under Instruction Control bit 4 the success of the WRITE operation can be moni- tored. In case of corrupt data bit 4 will be set volatile to Automatic RECALL to SRAM on Power Up high. With Secure READ operation the ANV32C91A Unlimited RECALL Cycles calculates the correct 2 Byte CRC parallel to data 100k STORE Cycles transfer. The 2 Byte CRC is transmitted after 64 Bytes of data have been transmitted. 100-Year Non-volatile Data Retention Data transfers automatically to the non-volatile storage Wide range 3.0V to 3.6V Power Supply cells when power loss is detected or in any brown out Commercial and Industrial Temperatures situation (the PowerStore operation). On power up, 8-pin 150 mil SOIC and DFN Packages data is automatically restored to the SRAM (the Power Up Recall operation). RoHS-Compliant Both STORE and RECALL operations are also avail- DESCRIPTION able under instruction control. The Anvo-Systems Dresden ANV32C91A is a 512kb BLOCK WRITE Protection is enabled by programming serial SRAM with a non-volatile SONOS storage ele- the status register with one of four options to protect ment included with each memory cell, organized as blocks. 64k words of 8 bits each. The devices are accessed by a high speed SPI-compatible bus. The ANV32C91A is BLOCK DIAGRAM FLASH Array 512 x 1024 V Power CC Control STORE VSS SRAM RECALL Array Store/ Recall 512 x 1024 Control Column I/O Data IO Register E Column Decoder HOLD Instruction Decode Control Logic SO Instruction Register SI Address Counter / Decoder SCK This product conforms to Anvo-Systems Dresden specifi- Document Control Nr. 020 Rev 1.0 cations 1 September, 2018 Row Deco derANV32C91A PIN CONFIGURATION PIN DESCRIPTIONS Signal Name Signal Description E 8 VCC 1 7 SO Chip Enable 2 E HOLD 6 SCK VCAP 3 SCK Serial Clock 5 VSS 4 SI Serial Input SI Serial Output SO Hold (Suspends Serial Top View HOLD Input) 8-pin SOP 150 mil or DFN VCC Power Supply Voltage VCAP Capacitor Voltage VSS Ground Serial Interface Description Master: The device that generates the serial clock. pin (SO) will remain in a high impedance state until the falling edge of E is detected. This will re-initialize the Slave: Because the Serial Clock pin (SCK) is always serial communication. an input, the device always operates as a slave. Chip Enable: The device is selected when the E pin is Transmitter/Receiver: The device has separate pins low. When the device is not selected (E pin is high), designated for data transmission (SO) and reception data will not be accepted via the SI pin, and the serial (SI). output pin (SO) will remain in a high impedance state. Unless an internal Write cycle is in progress the device Serial Output: The SO pin is used to transfer data will be in the Standby mode. Driving Chip Enable (E) serially out of the device. During a read cycle data is Low enables the device, placing it in the active power shifted out on this pin after the falling edge of the Serial mode. After Power-up a falling edge on Chip Enable Clock. (E) is required prior to the start of any instruction. Serial Input: The SI pin is used to transfer data serially Write Protect: The main purpose of this input signal is into the device. It receives instructions, addresses, and to freeze the size of the area of memory that is pro- data. Data is latched on the rising edge of the Serial tected against Write instructions (as specified by the Clock. values in the BP1 and BP0 bits of the Status Register) Serial Clock: The SCK pin is used to synchronize the and the selected PowerStore mode. This pin must be communication between a master and the device. driven either High or Low, and must be stable during all Instructions, addresses, or data, present on the SI pin, write operations. In case the Write Protect pin is not are latched on the rising edge of the clock input, while available the part cannot be hardware protected (inter- data on the SO pin is changed after the falling edge of nal high). the clock input. Hold: The HOLD pin is used in conjunction with the E MSB: The Most Significant Bit (MSB) is the first bit pin to select the device. When the device is selected transmitted and received. and a serial sequence is underway, HOLD can be used to pause the serial communication with the master Serial Op-Code: After the device is selected with E device without resetting the serial sequence. going low, the first byte will be received. This byte Buffer Cap: The VCAP pin provides the necessary contains the op-code that defines the operations to be energy for the PowerStore operation, via an external performed. capacitor. Invalid Op-Code: If an invalid op-code is received, no data will be shifted into the device, and the serial output Document Control Nr. 020 Rev 1.0 Anvo-Systems Dresden September, 2018 2 SOP/ DFN