ANV32C91W Anvo-Systems Dresden 512kb Serial SPI nvSRAM ANV32C91WC91W is enabled through the Chip FEATURES Enable pin (E) and accessed via a 3-wire interface con- compatible with Serial Peripheral Interface (SPI) sisting of Serial Data Input (SI), Serial Data Output Supports SPI Modes 0 and 3 (SO) and Serial Clock (SCK). All programming cycles 66MHz clock rate are self-timed, and no separate ERASE cycle is required before STORE. Block Write Protection The serial SRAM provides the fast access & cycle Write Disable Instruction for Software Data Pro- times, ease of use and unlimited read & write endur- tection ance of a normal SRAM. Dedicated safety features Secure WRITE supporting high data accuracy. Secure READ With Secure WRITE operation the ANV32C91W Hibernate Mode for low Standby Current accepts address and data only when the correct 2 Byte CRC, generated from the 16 bit address and 64 Byte Unlimited Read/Write Endurance data, is transmitted. Corrupt data can not overwrite Automatic Non-volatile STORE on Power Down existing memory content and even valid data would not Non-Volatile STORE under Instruction Control overwrite on a corrupted address. With status register bit 4 the success of the WRITE operation can be moni- Automatic RECALL to SRAM on Power Up tored. In case of corrupt data bit 4 will be set volatile to Unlimited RECALL Cycles high. With Secure READ operation the ANV32C91W 100k STORE Cycles calculates the correct 2 Byte CRC parallel to data transfer. The 2 Byte CRC is transmitted after 64 Bytes 100-Year Non-volatile Data Retention of data have been transmitted. Wide range 2.7V to 3.6V Power Supply Data transfers automatically to the non-volatile storage Commercial and Industrial Temperatures cells when power loss is detected or in any brown out 8-pin 150 mil SOIC and DFN Packages situation (the PowerStore operation). On power up, data is automatically restored to the SRAM (the Power RoHS-Compliant Up Recall operation). DESCRIPTION Both STORE and RECALL operations are also avail- The Anvo-Systems Dresden ANV32C91W is a 512kb able under instruction control. serial SRAM with a non-volatile SONOS storage ele- BLOCK WRITE Protection is enabled by programming ment included with each memory cell, organized as the status register with one of four options to protect 64k words of 8 bits each. The devices are accessed by blocks. a high speed SPI-compatible bus. The BLOCK DIAGRAM FLASH Array 512 x 1024 V Power CC Control STORE VSS SRAM RECALL Array Store/ Recall 512 x 1024 Control Column I/O Data IO Register E Column Decoder HOLD Instruction Decode Control Logic SO Instruction Register SI Address Counter / Decoder SCK This product conforms to Anvo-Systems Dresden specifi- Document Control Nr. 009 Rev 2.7 cations 1 September, 2017 Row Deco derANV32C91W PIN CONFIGURATION PIN DESCRIPTIONS Signal Name Signal Description E 8 VCC 1 7 SO Chip Enable 2 E HOLD 6 SCK VCAP 3 SCK Serial Clock 5 VSS 4 SI Serial Input SI Serial Output SO Hold (Suspends Serial Top View HOLD Input) 8-pin SOP 150 mil or DFN VCC Power Supply Voltage VCAP Capacitor Voltage VSS Ground pin (SO) will remain in a high impedance state until the Serial Interface Description falling edge of E is detected. This will re-initialize the serial communication. Master: The device that generates the serial clock. Chip Enable: The device is selected when the E pin is Slave: Because the Serial Clock pin (SCK) is always low. When the device is not selected (E pin is high), an input, the device always operates as a slave. data will not be accepted via the SI pin, and the serial Transmitter/Receiver: The device has separate pins output pin (SO) will remain in a high impedance state. designated for data transmission (SO) and reception Unless an internal Write cycle is in progress the device (SI). will be in the Standby mode. Driving Chip Enable (E) Low enables the device, placing it in the active power Serial Output: The SO pin is used to transfer data mode. After Power-up a falling edge on Chip Enable serially out of the device. During a read cycle data is (E) is required prior to the start of any instruction. shifted out on this pin after the falling edge of the Serial Clock. Write Protect: The main purpose of this input signal is to freeze the size of the area of memory that is pro- Serial Input: The SI pin is used to transfer data serially tected against Write instructions (as specified by the into the device. It receives instructions, addresses, and values in the BP1 and BP0 bits of the Status Register) data. Data is latched on the rising edge of the Serial and the selected PowerStore mode. This pin must be Clock. driven either High or Low, and must be stable during all write operations. In case the Write Protect pin is not Serial Clock: The SCK pin is used to synchronize the available the part cannot be hardware protected (inter- communication between a master and the device. nal high). Instructions, addresses, or data, present on the SI pin, are latched on the rising edge of the clock input, while Hold: The HOLD pin is used in conjunction with the E data on the SO pin is changed after the falling edge of pin to select the device. When the device is selected the clock input. and a serial sequence is underway, HOLD can be used to pause the serial communication with the master MSB: The Most Significant Bit (MSB) is the first bit device without resetting the serial sequence. transmitted and received. Buffer Cap: The VCAP pin provides the necessary Serial Op-Code: After the device is selected with E energy for the PowerStore operation, via an external going low, the first byte will be received. This byte capacitor. contains the op-code that defines the operations to be Connecting to the SPI Bus performed. These devices are fully compatible with the SPI pro- Invalid Op-Code: If an invalid op-code is received, no tocol. data will be shifted into the device, and the serial output All instructions, addresses and input data bytes are Document Control Nr. 009 Rev 2.7 Anvo-Systems Dresden September, 2017 2 SOP/ DFN