ANV32E61A Anvo-Systems Dresden 64kb Serial SPI nvSRAM FEATURES DESCRIPTION The Anvo-Systems Dresden ANV32E61A is a 64kb compatible with Serial Peripheral Interface (SPI) serial SRAM with a non-volatile SONOS storage ele- ment included with each memory cell, organized as 8k Supports SPI Modes 0 and 3 words of 8 bits each. The devices are accessed by a high speed SPI-compatible bus. The ANV32E61A is 66MHz clock rate enabled through the Chip Enable pin (E) and accessed Block Write Protection via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO) and Serial Clock (SCK). Secure WRITE All programming cycles are self-timed, and no separate ERASE cycle is required before STORE. Secure READ The serial SRAM provides the fast access & cycle 2Byte User Serial Number times, ease of use and unlimited read & write endur- ance of a normal SRAM. Dedicated safety features Hibernate Mode for low Standby Current supporting high data accuracy. Page and block rollover options With Secure WRITE operation the ANV32E61A accepts address and data only when the correct 2 Byte Unlimited Read/Write Endurance CRC, generated from the 13 bit address and 32 Byte data, is transmitted. Corrupt data cannot overwrite Automatic Non-volatile STORE on Power Down existing memory content and even valid data would not Non-Volatile STORE under Instruction Control overwrite on a corrupted address. With status register bit 4 the success of the WRITE operation can be moni- Automatic RECALL to SRAM on Power Up tored. In case of corrupt data bit 4 will be set volatile to high. With Secure READ operation the ANV32E61A Unlimited RECALL Cycles calculates the correct 2 Byte CRC parallel to data transfer. The 2 Byte CRC is transmitted after 32 Bytes 100k STORE Cycles of data have been transmitted. 100-Year Non-volatile Data Retention Data transfers automatically to the non-volatile storage cells when power loss is detected or in any brown out 3.0V to 3.6V Power Supply situation (the PowerStore operation). On power up, data is automatically restored to the SRAM (the Power Commercial and Industrial Temperatures Up Recall operation). 8-pin 150 mil SOIC and DFN Packages Both STORE and RECALL operations are also avail- able under instruction control. RoHS-Compliant BLOCK WRITE Protection is enabled by programming the status register with one of four options to protect blocks. A 2 Byte non-volatile register supports the option of a 2 Byte user defined serial number. This register is under customer control only. Status register bit 5 will control page and block roll over modes. This product conforms to Anvo-Systems Dresden specifications Document Control Nr. 005 Rev 3.0 1 October, 2016ANV32E61A Anvo-Systems Dresden BLOCK DIAGRAM FLASH Array 256 x 256 VCC Power VCAP Store Control V SS SRAM Recall Array Store / 256 x 256 Recall Control Data IO Register Column I/O Column Decoder E HOLD Instruction Decode SO Control Logic SI SCK Address Counter / Decoder PIN CONFIGURATION PIN DESCRIPTIONS 8 VCC E 1 Signal Name Signal Description 7 SO 2 HOLD Chip Enable E 6 VCAP 3 SCK 5 VSS 4 SI SCK Serial Clock Serial Input SI Top View Serial Output SO Hold (Suspends Serial HOLD Input) 8-pin SOP 150 mil or DFN VCC Power Supply Voltage VCAP Capacitor Voltage VSS Ground data. Data is latched on the rising edge of the Serial Serial Interface Description Clock. Master: The device that generates the serial clock. Serial Clock: The SCK pin is used to synchronize the communication between a master and the device. Slave: Because the Serial Clock pin (SCK) is always Instructions, addresses, or data, present on the SI pin, an input, the device always operates as a slave. are latched on the rising edge of the clock input, while Transmitter/Receiver: The device has separate pins data on the SO pin is changed after the falling edge of designated for data transmission (SO) and reception the clock input. (SI). MSB: The Most Significant Bit (MSB) is the first bit Serial Output: The SO pin is used to transfer data transmitted and received. serially out of the device. During a read cycle data is Serial Op-Code: After the device is selected with E shifted out on this pin after the falling edge of the Serial going low, the first byte will be received. This byte Clock. contains the op-code that defines the operations to be Serial Input: The SI pin is used to transfer data serially performed. into the device. It receives instructions, addresses, and This product conforms to Anvo-Systems Dresden specifications Document Control Nr. 005 Rev 3.0 2 October, 2016 SOP/ DFN Row Decoder