ATF-331M4 Low Noise Pseudomorphic HEMT in a Miniature Leadless Package Data Sheet Features Description Low noise figure Avago Technologiess ATF-331M4 is a high linearity, low noise pHEMT housed in a miniature leadless package. Excellent uniformity in product specifications 1600 micron gate width The ATF-331M4s small size and low profile makes it ideal for the design of hybrid modules and other Miniature leadless package 1.4 mm x 1.2 mm x 0.7 mm space-constraint devices. Tape-and-reel packaging option available Based on its featured performance, ATF-331M4 is ideal for the first or second stage of base station LNA Specifications due to the excellent combination of low noise figure 2 GHz 4V, 60 mA (Typ.) 1 and enhanced linearity . The device is also suitable for applications in Wireless LAN, WLL/RLL, MMDS, 0.6 dB noise figure and other systems requiring super low noise figure 15 dB associated gain with good intercept in the 450 MHz to 10 GHz frequency range. 19 dBm output power at 1 dB gain compression rd 31 dBm output 3 order intercept Note: 1. From the same PHEMT FET family, the smaller geometry ATF-34143 may also be considered for the higher gain performance, particularly in the Applications higher frequency band (1.8 GHz and up). Tower mounted amplifier, low noise amplifier and driver amplifier for GSM/TDMA/CDMA base stations LNA for WLAN, WLL/RLL, MMDS and wireless data MiniPak 1.4 mm x 1.2 mm Package infrastructures General purpose discrete PHEMT for other ultra low noise applications Pin Connections and Package Marking Drain Source Pin 4 Pin 3 Px Gate Source Pin 2 Pin 1 Note: Top View. Package marking provides orientation, product identification and date code. P = Device Type Code x = Date code character. A different character is assigned for each month and year. Px 1 ATF-331M4 Absolute Maximum Ratings Notes: Absolute 1. Operation of this device above any one of Symbol Parameter Units Maximum these parameters may cause permanent damage. 2 V Drain-Source Voltage V 5.5 DS 2. Assumes DC quiescent conditions. 2 3. V = 0 V V Gate-Source Voltage V-5 GS GS 4. Source lead temperature is 25C. Derate 2 V Gate Drain Voltage V-5 GD 5 mW/C for T > 40C. L 2 3 5. Please refer to failure rates in reliability data I Drain Current mA I DS diss sheet to assess the reliability impact of 4 P Total Power Dissipation mW 400 diss running devices above a channel temperature of 140C. P RF Input Power dBm 20 in max. 6. Thermal resistance measured using 150C 5 T Channel Temperature C 160 Liquid Crystal Measurement method. CH T Storage Temperature C -65 to 160 STG 6 Thermal Resistance C/W 200 jc 500 +0.6 V 400 300 0 V 200 100 -0.6 V Note: 0 7. Under large signal conditions, V may swing GS 02 4 6 8 positive and the drain current may exceed V (V) DS I . These conditions are acceptable as long dss 7 Figure 1. Typical Pulsed I-V Curves . as the Maximum P and P ratings are diss in max (V = -0.2 V per step) not exceeded. GS 8, 9 Product Consistency Distribution Charts 100 150 120 Cpk = 1.05 Cpk = 1.00 Cpk = 4.37 Stdev = 0.07 Stdev = 1.07 Stdev = 1.11 100 120 80 80 90 60 -3 Std +3 Std -3 Std +3 Std -3 Std +3 Std 60 40 60 40 20 30 20 0 0 0 28 30 32 34 36 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 13 14 15 16 17 OIP3 (dBm) GAIN (dB) NF (dBm) Figure 3. OIP3 2 GHz, 4 V, 60 mA. Figure 4. Gain 2 GHz, 4 V, 60 mA. Figure 2. NF 2 GHz, 4 V, 60 mA. LSL = 28.5, Nominal = 31.0, USL = 36.0 LSL = 13.5, Nominal = 15.0, USL = 16.5 LSL = 28.5, Nominal = 0.6, USL = 0.8. Notes: 8. Distribution data sample size is 349 samples from 4 different wafers. Future wafers allocated to this product may have nominal values anywhere within the upper and lower spec limits. 9. Measurements made on production test board. This circuit represents a trade-off between an optimal noise match and a realizeable match based on production test requirements. Circuit losses have been de-embedded from actual measurements. 2 I (mA) DS