ATF-511P8
[1]
High Linearity Enhancement Mode Pseudomorphic HEMT
2 [3]
in 2x2 mm LPCC Package
Data Sheet
Description Features
Avago Technologiess ATF-511P8 is a single-voltage high
Single voltage operation
linearity, low noise E-pHEMT housed in an 8-lead JEDEC-
High linearity and P1dB
[3]
standard leadless plastic chip carrier (LPCC ) package.
Low noise fi gure
The device is ideal as a high linearity, low-noise, medium-
power amplifi er. Its operating frequency range is from 50
Excellent uniformity in product specifi cations
MHz to 6 GHz.
Small package size:
2.0 x 2.0 x 0.75 mm
The thermally effi cient package measures only 2 mm
[2]
x 2 mm x 0.75 mm. Its backside metalization provides
Point MTTF > 300 years
excellent thermal dissipation as well as visual evidence
MSL-1 and lead-free
of solder refl ow. The device has a Point MTTF of over 300
years at a mounting temperature of +85C. All devices Tape-and-reel packaging option available
are 100% RF & DC tested.
Specifi cations
Notes:
2 GHz; 4.5V, 200 mA (Typ.)
1. Enhancement mode technology employs a single positive V ,
gs
eliminating the need of negative gate voltage associated with
41.7 dBm output IP3
conventional depletion mode devices.
2. Refer to reliability datasheet for detailed MTTF data.
30 dBm output power at 1 dB gain compression
3. Conforms to JEDEC reference outline MO229 for DRP-N.
1.4 dB noise fi gure
4. Linearity Figure of Merit (LFOM) is essentially OIP3 divided by DC
bias power.
14.8 dB gain
[4]
12.1 dB LFOM
Pin Connections and Package Marking
69% PAE
Pin 8 Pin 1 (Source)
Pin 7 (Drain) Pin 2 (Gate)
Applications
Pin 6 Pin 3
Front-end LNA Q2 and Q3 driver or pre-driver amplifi er
Pin 5 Pin 4 (Source)
for Cellular/PCS and WCDMA wireless infrastructure
Bottom View Driver amplifi er for WLAN, WLL/RLL and MMDS
applications
Pin 1 (Source) Pin 8
General purpose discrete E-pHEMT for other high
Pin 2 (Gate) Pin 7 (Drain)
linearity applications
1Px
Pin 3 Pin 6
Pin 4 (Source) Pin 5
Top View
Note:
Package marking provides orientation and identifi cation:
1P = Device Code
x = Date code indicates the month of manufacture.
Source
(Thermal/RF Gnd)[1]
ATF-511P8 Absolute Maximum Ratings
Notes:
Absolute 1. Operation of this device in excess of any one
of these parameters may cause permanent
Symbol Parameter Units Maximum
damage.
[2]
2. Assumes DC quiescent conditions.
V DrainSource Voltage V 7
DS
3. Board (package belly) temperatureT is
B
[2]
V Gate Source Voltage V -5 to 1
GS
25C. Derate 30 mW/C for T > 50C.
B
[2] 4. With 10 Ohm series resistor in gate supply
V Gate Drain Voltage V -5 to 1
GD
and 3:1 VSWR.
[2]
I Drain Current A 1
5. Channel-to-board thermal resistance
DS
measured using 150C Liquid Crystal
I Gate Current mA 46
GS
Measurement method.
[3]
P Total Power Dissipation W 3 6. Device can safely handle +30dBm RF Input
diss
Power provided I limited to 46mA. I at
GS GS
[4]
P RF Input Power dBm +30
in max.
P drive level is bias circuit dependent.
1dB
T Channel Temperature C 150
CH
T Storage Temperature C -65 to 150
STG
[5]
Thermal Resistance C/W 33
ch_b
[6,7]
Product Consistency Distribution Charts at 2 GHz, 4.5V, 200 mA
200
240
1000
0.8 V
Cpk = 3.24
Cpk = 1.66
900
200
Stdev = 0.6 Stdev = 0.15
160
800
0.7 V
700
160
120
600
+3 Std
-3 Std -3 Std +3 Std
500 120
0.6 V
400 80
80
300
200 40
40
0.5 V
100
0
0 0
02 4 6 8 35 38 41 44 47 28 29 30 31
OIP3 (dBm)
P1dB (dBm)
V (V)
DS
Figure 2. OIP3 LSL = 38.5, Nominal = 41.7.
Figure 3. P1dB LSL = 28.5, Nominal = 30.
Figure 1. Typical I-V Curves (V = 0.1 per step).
gs
150 160
Cpk = 1.4 Cpk = 3.03
Stdev = 0.31 Stdev = 1.85
120
120
90
-3 Std +3 Std -3 Std +3 Std
80
60
40
30
0 0
13 14 15 16 17 52 57 62 67 72 77 82
GAIN (dB) PAE (%)
Figure 4. Gain LSL = 13.5, Figure 5. PAE LSL = 52, Nominal = 68.9.
Nominal = 14.8, USL = 16.5.
Notes:
6. Distribution data sample size is 400 samples taken from 4 diff erent 7. Measurements are made on production test board, which represents
a trade-off between optimal OIP3, P1dB and VSWR. Circuit losses
wafers and 3 diff erent lots. Future wafers allocated to this product
may have nominal values anywhere between the upper and lower have been de-embedded from actual measurements.
limits.
2
I (mA)
DS