ATF-521P8 1 High Linearity Enhancement Mode Pseudomorphic HEMT 2 3 in 2x2 mm LPCC Package Data Sheet Description Features Avago Technologies ATF521P8 is a single voltage high Single voltage operation linearity, low noise EpHEMT housed in an 8lead JEDEC High linearity and P1dB 3 standard leadless plastic chip carrier (LPCC ) package. Low noise figure The device is ideal as a mediumpower, highlinearity amplifier. Its operating frequency range is from 50 MHz Excellent uniformity in product specifications to 6 GHz. 3 Small package size: 2.0 x 2.0 x 0.75 mm 2 The thermally efficient package measures only 2mm Point MTTF > 300 years x 2mm x 0.75mm. Its backside metalization provides MSL1 and leadfree excellent thermal dissipation as well as visual evidence Tapeand r eel packaging option available of solder reflow. The device has a Point MTTF of over 300 years at a mounting temperature of +85C. All Specifications devices are 100% RF & DC tested. 2 GHz 4.5V, 200 mA (Typ.) Pin Connections and Package Marking 42 dBm output IP3 26.5 dBm output power at 1 dB gain compression Pin 8 Pin 1 (Source) 1.5 dB noise figure Pin 7 (Drain) Pin 2 (Gate) 17 dB Gain Pin 6 Pin 3 4 Pin 5 Pin 4 (Source) 12.5 dB LFOM Bottom View Applications Pin 1 (Source) Pin 8 Front end LNA Q2 and Q3, driver or pre driver ampliefi r for Cellular/PCS and WCDMA wireless infrastructure Pin 2 (Gate) Pin 7 (Drain) 2Px Driver ampliefi r for WLAN, WLL/RLL and MMDS applica Pin 3 Pin 6 tions Pin 4 (Source) Pin 5 General purpose discrete E pHEMT for other high linear Top View ity applications Note: Package marking provides orientation and identification 2P = Device Code Attention: Observe precautions for x = Month code indicates the month of manufacture. handling electrostatic sensitive devices. ESD Machine Model (Class A) Note: ESD Human Body Model (Class 1C) 1. Enhancement mode technology employs a single positive V , gs Refer to Avago Technologies Application Note eliminating the need of negative gate voltage associated with A004R: Electrostatic Discharge Damage and Control. conventional depletion mode devices. 2. Refer to reliability datasheet for detailed MTTF data 3. Conform to JEDEC reference outline MO229 for DRPN 4. Linearity Figure of Merit (LFOM) is essentially OIP3 divided by DC bias power. Source (Thermal/RF Gnd) 1 ATF-521P8 Absolute Maximum Ratings Absolute Symbol Parameter Units Maximum 2 V Drain Source Voltage V 7 DS 2 V Gate Source Voltage V 5 to 1 GS 2 V Gate Drain Voltage V 5 to 1 GD 2 I Drain Current mA 500 DS I Gate Current mA 46 GS 3 P Total Power Dissipation W 1.5 diss P RF Input Power dBm 27 in max. T Channel Temperature C 150 CH T Storage Temperature C 65 to 150 STG 4 Thermal Resistance C/W 45 ch b Notes: 1. Operation of this device in excess of any one of these parameters may cause permanent damage. 2. Assumes DC quiescent conditions. 3. Board (package belly) temperatureT is 25C. Derate 22 mW/C for T > 83C. B B 4. Channel to board thermal resistance measured using 150C Liquid Crystal Measurement method. 5. Device can safely handle +27dBm RF Input Power provided IGS is limited to 46mA. IGS at P1dB drive level is bias circuit dependent. 5, 6 Product Consistency Distribution Charts 600 180 150 Stdev = 0.19 Cpk = 0.86 0.8V Stdev = 1.32 500 150 120 0.7V 120 400 90 -3 Std +3 Std -3 Std +3 Std 90 300 60 Vgs = 0.6V 60 200 30 30 100 0.5V 0.4V 0 0 0 1 0 0.5 1.5 2 2.5 3 37 39 41 43 45 47 49 0 2 4 6 8 NF (dB) V (V) OIP3 (dBm) DS Figure 2. NF 2 GHz, 4.5 V, 200 mA. Figure 1. Typical I-V Curves. Figure 3. OIP3 2 GHz, 4.5 V, 200 mA. (V = 0.1 V per step) Nominal = 1.5 dB. Nominal = 41.9 dBm, LSL = 38.5 dBm. GS 180 300 Cpk = 2.13 Cpk = 4.6 Stdev = 0.21 Stdev = 0.11 150 250 120 200 -3 Std +3 Std -3 Std +3 Std 90 150 60 100 30 50 0 0 15 16 17 18 19 26 25 25.5 26.5 27 27.5 GAIN (dB) P1dB (dBm) Figure 4. Gain 2 GHz, 4.5 V, 200 mA. Figure 5. P1dB 2 GHz, 4.5 V, 200 mA. Nominal = 17.2 dB, LSL = 15.5 dB, Nominal = 26.5 dBm, LSL = 25 dBm. USL = 18.5 dB. Notes: 5. Distribution data sample size is 500 samples taken from 5 different wafers. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 6. Measurements are made on production test board, which represents a trade off between optimal OIP3, P1dB and VSWR. Circuit losses have been deembedded from actual measurements. 2 I (mA) DS