ATF-54143 Low Noise Enhancement Mode Pseudomorphic HEMT in a Surface Mount Plastic Package Data Sheet Description Features High linearity performance Avago Technologies ATF-54143 is a high dynamic range, low noise, E-PHEMT housed in a 4-lead SC-70 (SOT-343) 1 Enhancement Mode Technology surface mount plastic package. Low noise fi gure The combination of high gain, high linearity and low Excellent uniformity in product specifi cations noise makes the ATF-54143 ideal for cellular/PCS base 800 micron gate width stations, MMDS, and other systems in the 450 MHz to 6 Low cost surface mount small plastic package SOT- GHz frequency range. 343 (4 lead SC-70) Tape-and-Reel packaging option available Surface Mount Package SOT-343 Lead-free option available. Specifi cations 2 GHz 3V, 60 mA (Typ.) rd 36.2 dBm output 3 order intercept 20.4 dBm output power at 1 dB gain compression Pin Connections and Package Marking 0.5 dB noise fi gure DRAIN 16.6 dB associated gain SOURCE Applications SOURCE GATE Low noise amplifi er for cellular/PCS base stations LNA for WLAN, WLL/RLL and MMDS applications Note: General purpose discrete E -PHEMT for other ultra low Top View. Package marking provides orientation and identifi cation noise applications 4F = Device Code Note: x = Date code character 1. Enhancement mode technology requires positive Vgs, thereby identifi es month of manufacture. eliminating the need for the negative gate voltage associated with conventional depletion mode devices. Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model (Class A) ESD Human Body Model (Class 1A) Refer to Avago Application Note A004R: Electrostatic Discharge Damage and Control. 4Fx 1 ATF-54143 Absolute Maximum Ratings Absolute Symbol Parameter Units Maximum 2 V Drain - Source Voltage V 5 DS 2 Gate - Source Voltage V -5 to 1 V GS 2 V Gate Drain Voltage V -5 to 1 GD 2 Drain Current mA 120 I DS 3 P Total Power Dissipation mW 725 diss 5 (ON mode) RF Input Power (Vds=3V, Ids=60mA) dBm 20 P in max. P (OFF mode) RF Input Power (Vd=0, Ids=0A) dBm 20 in max. 5 Gate Source Current mA 2 I GS Channel Temperature C 150 T CH Storage Temperature C -65 to 150 T STG 4 Thermal Resistance C/W 162 jc Notes: 120 0.7V 1. Operation of this device in excess of any one of these parameters may cause permanent damage. 100 2. Assumes DC quiescent conditions. 0.6V 3. Source lead temperature is 25C. Derate 6.2 mW/C for T > 33C. L 80 4. Thermal resistance measured using 150C Liquid Crystal Measure- ment method. 60 0.5V 5. The device can handle +20 dBm RF Input Power provided I is GS 40 limited to 2 mA. I at P drive level is bias circuit dependent. GS 1dB See application section for additional information. 20 0.4V 0.3V 0 02143756 V (V) DS Figure 1. Typical I-V Curves. (V = 0.1 V per step) GS 6, 7 Product Consistency Distribution Charts 160 200 160 Cpk = 0.77 Cpk = 1.35 Cpk = 1.67 Stdev = 1.41 Stdev = 0.4 Stdev = 0.073 160 120 120 120 -3 Std +3 Std -3 Std +3 Std 80 80 80 40 40 40 0 0 0 30 32 34 36 38 40 42 14 15 16 17 18 19 0.25 0.45 0.65 0.85 1.05 GAIN (dB) OIP3 (dBm) NF (dB) Figure 3. Gain 2 GHz, 3 V, 60 mA. Figure 2. OIP3 2 GHz, 3 V, 60 mA. Figure 4. NF 2 GHz, 3 V, 60 mA. USL = 18.5, LSL = 15, Nominal = 16.6 LSL = 33.0, Nominal = 36.575 USL = 0.9, Nominal = 0.49 Notes: 6. Distribution data sample size is 450 samples taken from 9 diff erent wafers. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 7. Measurements made on production test board. This circuit represents a trade-off between an optimal noise match and a realizeable match based on production test equipment. Circuit losses have been de-embedded from actual measurements. 2 I (mA) DS