ATF-58143 Low Noise Enhancement Mode Pseudomorphic HEMT in a Surface Mount Plastic Package Data Sheet Description Features Low noise and high linearity performance Avago Technologies ATF-58143 is a high dynamic 1 range, low noise E-PHEMT housed in a 4-lead SC-70 Enhancement Mode Technology (SOT-343) surface mount plastic package. Excellent uniformity in product specifi cations The combination of high gain, high linearity and low Low cost surface mount small plastic package SOT- noise makes the ATF-58143 ideal as low noise ampli- 343 (4 lead SC-70) in Tape-and-Reel packaging option fi er for cellular/PCS/WCDMA base stations, wireless lo- available cal loop, and other applications that require low noise Lead-free option available and high linearity performance in the 450 MHz to 6 GHz frequency range. Specifi cations 2 GHz 3V, 30 mA (Typ.) Surface Mount Package SOT-343 rd 30.5 dBm output 3 order intercept 19 dBm output power at 1 dB 0.5 dB noise fi gure 16.5 dB associated gain Applications Q1 LNA for cellular/PCS/WCDMA base stations Pin Connections and Package Marking Q1, Q2 LNA and Pre-driver amplifi er for 34 GHz WLL Other low noise and high linearity applications at 450 DRAIN SOURCE MHz to 6 GHz Note: 1. Enhancement mode technology requires positive Vgs, thereby SOURCE GATE eliminating the need for the negative gate voltage associated with conventional depletion mode devices. Note: Top View. Package marking provides orientation and identifi cation Attention: Observe precautions for handling electrostatic sensitive devices. 8F = Device Code ESD Machine Model (Class A) x = Date code character ESD Human Body Model (Class 1A) identifi es month of manufacture. Refer to Avago Technologies Application Note A004R: Electrostatic Discharge Damage and Control. 8Fx 1 ATF-58143 Absolute Maximum Ratings Symbol Parameter Units AbsoluteMaximum 2 V Drain-SourceVoltage V5 DS 2 V Gate-SourceVoltage V -5to1 GS 2 V GateDrainVoltage V -5to1 GD 2 I DrainCurrent mA 100 DS 3 P TotalPowerDissipation mW 500 diss P RF InputPower inmax. (Vds=3V , Ids =30mA) dBm +20 (Vds=0V, Ids=0mA) dBm +20 (Vds=4V, Ids=30mA) dBm +20 5 I GateSourceCurrent mA 2 GS T ChannelTemperature C 150 CH T StorageTemperature C -65to150 STG 4 ThermalResistance C/W 162 jc Notes: 120 0.7V 1. Operation of this device above any one of these parameters may cause permanent damage. 100 2. Assumes DC quiescent conditions. 0.6V 3. Source lead temperature is 25C. Derate 6.2 mW/C for T > 33C. L 80 4. Thermal resistance measured using 150C Liquid Crystal Measure- ment method. 60 5. The device can handle +13 dBm RF Input Power provided I is limited 0.5V GS 40 to 2 mA. I at P drive level is bias circuit dependent. See applications GS 1dB section for additional information. 20 0.4V 0.3V 0 071 2 3 4 5 6 V (V) DS Figure 1. Typical I-V Curves (V =0.1V per step) GS 6, 7 Product Consistency Distribution Charts -150 Cpk=2.735 Cpk=1.953 Cpk=1.036 Stdev=0.049 Stdev=0.2610 Stdev=0.509 -125 -100 -75 -50 -25 0 28 29 30 31 32 33 34 15 16 17 18 0.3 0.4 0.5 0.6 0.7 0.8 GAIN (dB) OIP3 (dBm) NF (dB) Figure 3. Gain 3V, 30 mA. Figure 4. OIP3 3V, 30 mA. Figure 2. NF 3V, 30 mA. USL = 18.5, LSL = 15, Nominal = 16.5 LSL = 29, Nominal = 30.5 USL = 0.9, Nominal = 0.5 Notes: 6. Distribution data sample size is 500 samples taken from 3 diff erent wafers. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 7. Measurements made on production test board. This circuit represents a trade-off between an optimal noise match and a realizeable match based on production test equipment. Circuit losses have been de-embedded from actual measurements. 2 I (mA) DS