PH1225AL NXP

PH1225AL N-channel 25 V 1.2 m logic level MOSFET in LFPAK Rev. 01 14 October 2009 Product data sheet 1. Product profile 1.1 General description Logic level N-channel MOSFET in LFPAK package qualified to 150 C. This product is for computing use only 1.2 Features and benefits Advanced TrenchMOS provides low Improved mechanical and thermal RDSon and low gate charge characteristics High efficiency gains in switching LFPAK provides maximum power power converters density in a Power SO8 package 1.3 Applications For computing use only 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit V drain-source voltage T 25 C T 150 C - - 25 V DS j j 1 I drain current T =25C V =10V - - 100 A D mb GS see Figure 1 P total power T = 25 C see Figure 2 - - 121 W tot mb dissipation T junction temperature -55 - 150 C j Avalanche ruggedness E non-repetitive V =10V T =25C - - 677 mJ DS(AL)S GS j(init) drain-source I = 100 A V 25 V D sup avalanche energy R =50 unclamped GS Dynamic characteristics Q gate-drain charge V = 4.5 V I =25A - 11.9 - nC GD GS D V =12V DS Q total gate charge - 50.6 - nC G(tot) see Figure 12 and 13 Static characteristics R drain-source V =10V I =15A --1.6 m DSon GS D on-state resistance T = 100 C see Figure 11 j V =10V I =15A -0.9 1.2 m GS D T = 25 C see Figure 10 j 1 Continuous current is limited by package.NXP Semiconductors PH1225AL N-channel 25 V 1.2 m logic level MOSFET in LFPAK 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1S source D 2S source 3S source G 4G gate mbb076 S mb D drain 142 3 SOT1023 (LFPAK2) 3. Ordering information Table 3. Ordering information Type number Package Name Description Version PH1225AL LFPAK2 Plastic single-ended surface-mounted package (LFPAK2) 4 leads SOT1023 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V drain-source voltage T 25 C T 150 C - 25 V DS j j V drain-gate voltage T 25 C T 150 C R =20k -25 V DGR j j GS V gate-source voltage -20 20 V GS 1 I drain current V =10 V T = 100 C see Figure 1 -100 A D GS mb 1 V =10 V T =25C see Figure 1 -100 A GS mb I peak drain current t 10 s pulsed T =25C see Figure 3 -815 A DM p mb P total power dissipation T =25C see Figure 2 -121 W tot mb T storage temperature -55 150 C stg T junction temperature -55 150 C j T peak soldering temperature - 260 C sld(M) Source-drain diode 1 I source current T =25C -100 A S mb I peak source current t 10 s pulsed T =25C - 815 A SM p mb Avalanche ruggedness E non-repetitive drain-source V =10 V T =25C I =100 A -677 mJ DS(AL)S GS j(init) D avalanche energy V 25 V R =50 unclamped sup GS 1 Continuous current is limited by package. PH1225AL 1 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 14 October 2009 2 of 12