PH1955L,115 NXP

PH1955L N-channel TrenchMOS logic level FET Rev. 02 25 February 2009 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Low conduction losses due to low Suitable for thermally demanding on-state resistance environments due to 175 C rating Suitable for logic level gate drive sources 1.3 Applications 12 V and 24 V loads General purpose power switching DC-to-DC convertors Motors, lamps and solenoids 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit V drain-source voltage T 25 C; T 175 C - - 55 V DS j j I drain current T =25C; V =5V; --40 A D mb GS see Figure 1; see Figure 3 P total power T = 25 C; see Figure 2 --75 W tot mb dissipation Dynamic characteristics Q gate-drain charge V =5V; I =25A; -8 -nC GD GS D V =44V; T =25C; DS j see Figure 9 Static characteristics R drain-source V =10V; I =25A; - 14.3 17.3 m DSon GS D on-state resistance T = 25 C; see Figure 7; j see Figure 8NXP Semiconductors PH1955L N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1S source mb D 2S source 3S source G 4G gate mbb076 S mb D mounting base; connected to 1234 drain SOT669 (LFPAK) 3. Ordering information Table 3. Ordering information Type number Package Name Description Version PH1955L LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 PH1955L_2 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 25 February 2009 2 of 12