ESD8004MUTAG ON Semiconductor

ESD8004 ESD Protection Diode Low Capacitance Array for High Speed Data Lines The ESD8004 is designed to protect high speed data lines from www.onsemi.com ESD. Ultralow capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed MARKING data lines. The flowthrough style package allows for easy PCB layout DIAGRAM and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as USB 3.0/3.1. UDFN10 4DM CASE 517BB Features Low Capacitance (0.35 pF Max, I/O to GND) 4D = Specific Device Code (tbd) Protection for the Following IEC Standards: M = Date Code IEC 6100042 (Level 4) = PbFree Package (Note: Microdot may be in either location) Low ESD Clamping Voltage SZ Prefix for Automotive and Other Applications Requiring Unique PIN CONFIGURATION AND SCHEMATIC Site and Control Change Requirements AECQ101 Qualified and PPAP Capable N/C N/C GND N/C N/C These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant 10 98 7 6 Typical Applications 1423 5 USB 3.0/3.1 I/O I/O GND I/O I/O eSATA DisplayPort I/O I/O I/O I/O Pin 1 Pin 2 Pin 4 Pin 5 MAXIMUM RATINGS (T = 25C unless otherwise noted) J Rating Symbol Value Unit Operating Junction Temperature Range T 55 to +125 C J Storage Temperature Range T 55 to +150 C stg Lead Solder Temperature T 260 C L Pins 3, 8 Maximum (10 Seconds) Note: Common GND Only Minimum of 1 GND connection required IEC 6100042 Contact (ESD) ESD 15 kV IEC 6100042 Air (ESD) ESD 15 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ORDERING INFORMATION Device Package Shipping ESD8004MUTAG UDFN10 3000 / Tape & (PbFree) Reel SZESD8004MUTAG UDFN10 3000 / Tape & (PbFree) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: November, 2017 Rev. 6 ESD8004/D =ESD8004 See Application Note AND8308/D for further description of survivability specs. ELECTRICAL CHARACTERISTICS I (T = 25C unless otherwise noted) A I PP Symbol Parameter V Working Peak Voltage RWM R DYN I Maximum Reverse Leakage Current V R RWM V Breakdown Voltage I BR T V V BR V V V C RWM HOLD I Test Current I V T R C I T V Holding Reverse Voltage HOLD I HOLD I Holding Reverse Current HOLD R Dynamic Resistance DYN R DYN I Maximum Peak Pulse Current PP I PP V Clamping Voltage I C PP V = V + (I * R ) C HOLD PP DYN V = V + (I * R ) C HOLD PP DYN ELECTRICAL CHARACTERISTICS (T = 25C unless otherwise specified) A Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage V I/O Pin to GND 3.3 V RWM Breakdown Voltage V I = 1 mA, I/O Pin to GND 5.5 7.0 V BR T Reverse Leakage Current I V = 3.3 V, I/O Pin to GND 1.0 A R RWM Holding Reverse Voltage V I/O Pin to GND 1.19 V HOLD Holding Reverse Current I I/O Pin to GND 25 mA HOLD Clamping Voltage (Note 1) V IEC6100042, 8 KV Contact See Figures 1 and 2 V C Clamping Voltage V 4.9 V I = 8 A IEC 6100042 Level 2 equivalent C PP TLP (Note 2) 4.5 I = 8 A (4 kV Contact, 4 kV Air) PP See Figures 5 through 8 I = 16 A 8.0 PP IEC 6100042 Level 4 equivalent 8.0 I = 16 A PP (8 kV Contact, 15 kV Air) Dynamic Resistance R I/O Pin to GND 0.40 DYN GND to I/O Pin 0.45 Junction Capacitance C V = 0 V, f = 1 MHz between I/O Pins and GND 0.30 0.35 pF J R (See Figures 9 & 10) V = 0 V, f = 2.5 GHz between I/O Pins and GND 0.25 0.30 R V = 0 V, f = 1 MHz, between I/O Pins 0.15 0.20 R Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. For test procedure see Figures 3 and 4 and application note AND8307/D. 2. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z = 50 , t = 100 ns, t = 4 ns, averaging window t = 30 ns to t = 60 ns. 0 p r 1 2 90 10 0 80 70 10 60 20 50 30 40 40 30 50 20 60 10 70 0 80 10 90 20 0 20 40 60 80 100 120 140 20 0 20 40 60 80 100 120 140 TIME (ns) TIME (ns) Figure 1. IEC6100042 +8 kV Contact ESD Figure 2. IEC6100042 8 kV Contact Clamping Voltage Clamping Voltage www.onsemi.com 2 VOLTAGE (V) VOLTAGE (V)