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The switch node has been internally connected to DS(on) GS D enable easy placement and routing of synchronous buck Max r = 4.7 m at V = 4.5 V, I = 18 A DS(on) GS D converters. The control MOSFET (Q1) and synchronous Q2: N-Channel TM SyncFET (Q2) have been designed to provide optimal power Max r = 1.2 m at V = 10 V, I = 41 A DS(on) GS D efficiency. Max r = 1.4 m at V = 4.5 V, I = 37 A DS(on) GS D Applications Low inductance packaging shortens rise/fall times, resulting in Computing lower switching losses Communications MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node General Purpose Point of Load ringing RoHS Compliant PAD10 PIN1 PIN1 V+(HSD) HSG LSG LSG HSG SW GR SW GR SW PAD9 GND(LSS) SW V+ V+ SW SW V+ SW V+ Bottom Top Power Clip 5X6 Pin Name Description Pin Name Description Pin Name Description 1 HSG High Side Gate 3,4,10 V+(HSD) High Side Drain 8 LSG Low Side Gate 2 GR Gate Return 5,6,7 SW Switching Node, Low Side Drain 9 GND(LSS) Low Side Source MOSFET Maximum Ratings T = 25 C unless otherwise noted A Symbol Parameter Q1 Q2 Units Note5 V Drain to Source Voltage 25 25 V DS V Gate to Source Voltage 12 12 V GS Drain Current -Continuous T = 25 C 60 110 C Note1a Note1b I -Continuous T = 25 C 20 41 A D A -Pulsed T = 25 C (Note 4) 75 160 A E Single Pulse Avalanche Energy (Note 3) 73 253 mJ AS Power Dissipation for Single Operation T = 25 C 21 42 C P W D Note1a Note1b Power Dissipation for Single Operation T = 25 C 2.1 2.3 A T , T Operating and Storage Junction Temperature Range -55 to +150 C J STG Thermal Characteristics R Thermal Resistance, Junction to Case 6.0 3.0 JC Note1a Note1b R Thermal Resistance, Junction to Ambient 60 55 C/W JA Note1c Note1d R Thermal Resistance, Junction to Ambient 130 120 JA 2013 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDPC8014S Rev.C7