SSM3K131TU TOSHIBA Field-Effect Transistor Silicon N-Channel MOS Type (U-MOS) SSM3K131TU High-Speed Switching Applications Unit: mm 4.5-V drive Low ON-resistance : R = 41.5 m (max) ( V = 4.5 V) on GS 2.10.1 : R = 27.6 m (max) ( V = 10 V) on GS 1.70.1 Absolute Maximum Ratings (Ta = 25C) 1 Characteristic Symbol Rating Unit 3 2 Drain-Source voltage V 30 V DSS Gate-Source voltage V 20 V GSS DC I (Note 1) 6.0 D Drain current A Pulse I (Note 1) 12.0 DP P (Note 2) 800 D Drain power dissipation P (Note 3) 500 mW D t = 10 s 1000 Channel temperature T 150 C 1: Gate ch 2: Source Storage temperature range T 55 to 150 C stg UFM 3: Drain Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly JEDEC even if the operating conditions (i.e. operating temperature/current/ voltage, etc.) are within the absolute maximum ratings. JEITA Please design the appropriate reliability upon reviewing the Toshiba TOSHIBA 2-2U1A Semiconductor Reliability Handbook (Handling Precautions/Derating Concept and Methods) and individual reliability data (i.e. reliability test Weight: 6.6mg (typ.) report and estimated failure rate, etc). Note 1: The junction temperature should not exceed 150C during use. 2 Note 2: Mounted on a ceramic board. (25.4 mm 25.4 mm 0.8 mm, Cu Pad: 645 mm ) 2 Note 3: Mounted on an FR4 board. (25.4 mm 25.4 mm 1.6 mm, Cu Pad: 645 mm ) Electrical Characteristics (Ta = 25C) Characteristic Symbol Test Conditions Min Typ. MaxUnit V I = 10 mA, V = 0 V 30 (BR) DSS D GS Drain-Source breakdown voltage V V I = 10 mA, V = -20 V 15 (BR) DSX D GS Drain cut-off current I V = 30 V, V = 0 V 1 A DSS DS GS Gate leakage current I V = 20 V, V = 0 V 0.1 A GSS GS DS Gate threshold voltage V V = 5 V, I = 1 mA 1.3 2.5 V th DS D Forward transfer admittance Y V = 5 V, I = 4 A (Note 4) 11.5 23.0 S fs DS D I = 4.0 A, V = 10 V (Note 4) 20.5 27.6 D GS Drainsource ON-resistance R m DS (ON) I = 2.0 A, V = 4.5 V (Note 4) 27.0 41.5 D GS Input capacitance C 450 iss Output capacitance C V = 15 V, V = 0 V, f = 1 MHz 120 pF oss DS GS Reverse transfer capacitance C 77 rss Total Gate Charge Q 10.1 g V = 15 V, I = 6.0 A DS D Gate-Source Charge Q 7.6 nC gs V = 10 V GS Gate-Drain Charge Q 2.5 gd Turn-on time t V = 15 V, I = 2.0 A, 21 on DD D Switching time ns Turn-off time t V = 0 to 4.5 V, R = 10 15 GS G off Drain-Source forward voltage V I = -6.0 A, V = 0 V (Note 4) -0.85 -1.2 V DSF D GS Note 4: Pulse test Start of commercial production 2008-09 1 2014-03-01 2.00.1 0.650.05 0.70.05 0.1660.05 +0.1 0.3 -0.05SSM3K131TU Switching Time Test Circuit (a) Test Circuit (b) V IN 4.5 V 90% 10% OUT 0 V 4.5 V IN (c) V V 0 OUT DD 10% 10 s V DD 90% V DS (ON) t t V = 15 V r f DD R = 10 G t t on off Duty 1% V : t , t < 5 ns IN r f Common Source Ta = 25C Marking Equivalent Circuit (top view) 3 3 KKJ 1 2 1 2 Handling Precaution When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that come into direct contact with devices should be made of antistatic materials. Usage Considerations Let V be the voltage applied between gate and source that causes the drain current (I ) to be low (1 mA for the th D SSM3K131TU). Then, for normal switching operation, V must be higher than V and V must be lower than GS(on) th, GS(off) V This relationship can be expressed as: V < V < V th. GS(off) th GS(on). Take this into consideration when using the device. 2 2014-03-01 R G