Si3430DV www.vishay.com Vishay Siliconix N-Channel 100 V (D-S) MOSFET FEATURES TSOP-6 Single S High-efficiency PWM optimized 4 D 100 % R tested g 5 D Material categorization: 6 for definitions of compliance please see www.vishay.com/doc 99912 Available 3 G (1, 2, 5, 6) D 2 D 1 D Top View PRODUCT SUMMARY (3) G V (V) 100 DS R max. () at V = 10 V 0.170 DS(on) GS R max. () at V = 6 V 0.185 DS(on) GS Q typ. (nC) 5.5 g (4) S I (A) 2.4 D Configuration Single N-Channel MOSFET ORDERING INFORMATION Package TSOP-6 Lead (Pb)-free Si3430DV-T1-E3 Lead (Pb)-free and halogen-free Si3430DV-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL 5 s STEADY STATE UNIT Drain-source voltage V 100 100 DS V Gate-source voltage V 20 20 GS T = 25 C 2.4 1.8 A a Continuous drain current (T = 175 C) I J D T = 85 C 1.7 1.3 A A Pulsed drain current I 88 DM Avalanche current I 66 AR L = 0.1 mH Repetitive avalanche energy (duty cycle 1 %) E 1.8 1.8 mJ AR a Continuous source current (diode conduction) I 1.7 1 A S T = 25 C 21.14 A a Maximum power dissipation P W D T = 85 C 1 0.59 A Operating junction and storage temperature range T , T -55 to +150 -55 to +150 C J stg THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYPICALMAXIMUMUNIT t 5 s 45 62.5 a Maximum junction-to-ambient R thJA Steady state 90 110 C/W Maximum junction-to-foot (drain) Steady state Rt 25 30 hJF Note a. Surface mounted on 1 x 1 FR4 board S19-0836-Rev. E, 30-Sep-2019 Document Number: 71235 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 Si3430DV www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP.MAX.UNIT Static Gate threshold voltage V V = V , I = 250 A 2 - 4.2 V GS(th) DS DS D Gate-body leakage I V = 0 V, V = 20 V - - 100 nA GSS DS GS V = 80 V, V = 0 V - - 1 DS GS Zero gate voltage drain current I A DSS V = 80 V, V = 0 V, T = 85 C - - 25 DS GS J a On-state drain current I V 5 V, V = 10 V 8 - - A D(on) DS GS V = 10 V, I = 2.4 A - 0.148 0.170 GS D a Drain-source on-state resistance R DS(on) V = 6 V, I = 2.3 A - 0.160 0.185 GS D a Forward transconductance g V = 15 V, I = 2.4 A - 7 - S fs DS D a Diode forward voltage V I = 1.7 A, V = 0 V - 0.8 1.2 V SD S GS b Dynamic Total gate charge Q -5.5 8.2 g Gate-source charge Q V = 50 V, V = 10 V, I = 2.4 A -1.5 - nC gs DS GS D Gate-drain charge Q -1.4 - gd Gate resistance R 1- 4 g Turn-on delay time t -9 20 d(on) Rise time t -11 20 r V = 50 V, R = 50 DD L ns I 1 A, V = 10 V, R = 6 Turn-off delay time t D GEN g -16 30 d(off) Fall time t -9 20 f Gate resistance R V = 0.1 V, f = 5 MHz - 2.8 - g GS Source-drain reverse recovery time t I = 1.7 A, di/dt = 100 A/s - 50 80 ns rr F Notes a. Pulse test pulse width 300 s, duty cycle 2 % b. Guaranteed by design, not subject to production testing Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S19-0836-Rev. E, 30-Sep-2019 Document Number: 71235 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000